CAT1162WI28 Datasheet CAT1161LI-25-G, CAT1162WI-30-G, CAT1162LI-30-G | P7-P9

CAT1161, CAT1162

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FUCTIONAL DESCRIPTION

The CAT1161/2 supports the I

C Bus data transmission

protocol. This Inter−Integrated Circuit Bus protocol defines

any device that sends data to the bus to be a transmitter and

any device receiving data to be a receiver. The transfer is

controlled by the Master device which generates the serial

clock and all START and STOP conditions for bus access.

Both the Master device and Slave device can operate as

either transmitter or receiver, but the Master device controls

which mode is activated.

C Bus Protocol

The features of the I

C bus protocol are defined as

follows:

1. Data transfer may be initiated only when the bus is

not busy.

2. During a data transfer, the data line must remain

stable whenever the clock line is high. Any

changes in the data line while the clock line is high

will be interpreted as a START or STOP condition.

START Condition

The START Condition precedes all commands to the

device, and is defined as a HIGH to LOW transition of SDA

when SCL is HIGH. The CAT1161/2 monitors the SDA and

SCL lines and will not respond until this condition is met.

STOP Condition

A LOW to HIGH transition of SDA when SCL is HIGH

determines the STOP condition. All operations must end

with a STOP condition.

Device Addressing

The Master begins a transmission by sending a START

condition. The Master sends the address of the particular

slave device it is requesting. The four most significant bits

of the 8−bit slave address are fixed as 1010.

The next three bits (Figure 6) define memory addressing.

For the CAT1161/2 the three bits define higher order bits.

The last bit of the slave address specifies whether a Read

or Write operation is to be performed. When this bit is set to

1, a Read operation is selected, and when set to 0, a Write

operation is selected.

After the Master sends a START condition and the slave

address byte, the CAT1161/2 monitors the bus and responds

with an acknowledge (on the SDA line) when its address

matches the transmitted slave address. The CAT1161/2 then

performs a Read or Write operation depending on the

R/W

bit.

Figure 5. Acknowledge Timing

ACKNOWLEDGE

RTSTA

SCL FROM

MASTER

DATA OUTPUT

FROM TRANSMITTER

DATA OUTPUT

FROM RECEIVER

Figure 6. Slave Address Bits

1 0 1 0 a10 a9 a8 R/W

Note: a8, a9 and a10 correspond to the address of the memory array address word.

CAT1161/2

Acknowledge

After a successful data transfer, each receiving device is

required to generate an acknowledge. The acknowledging

device pulls down the SDA line during the ninth clock cycle,

signaling that it received the 8 bits of data.

The CAT1161/2 responds with an acknowledge after

receiving a START condition and its slave address. If the

device has been selected along with a write operation, it

responds with an acknowledge after receiving each 8−bit

byte.

When the CAT1161/2 begins a READ mode it transmits

8 bits of data, releases the SDA line and monitors the line for

an acknowledge. Once it receives this acknowledge, the

CAT1161/2 will continue to transmit data. If no

acknowledge is sent by the Master, the device terminates

data transmission and waits for a STOP condition.

CAT1161, CAT1162

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WRITE OPERATIONS

Byte Write

In the Byte Write mode, the Master device sends the

START condition and the slave address information (with

the R/W

bit set to zero) to the Slave device. After the Slave

generates an acknowledge, the Master sends a 8−bit address

that is to be written into the address pointers of the

CAT1161/2. After receiving another acknowledge from the

Slave, the Master device transmits the data to be written into

the addressed memory location. The CAT1161/2

acknowledges once more and the Master generates the

STOP condition. At this time, the device begins an internal

programming cycle to non−volatile memory. While the

cycle is in progress, the device will not respond to any

request from the Master device.

Page Write

The CAT1161/2 writes up to 16 bytes of data in a single

write cycle, using the Page Write operation. The page write

operation is initiated in the same manner as the byte write

operation, however instead of terminating after the initial

byte is transmitted, the Master is allowed to send up to 15

additional bytes. After each byte has been transmitted, the

CAT1161/2 will respond with an acknowledge and

internally increment the lower order address bits by one. The

high order bits remain unchanged.

If the Master transmits more than 16 bytes before sending

the STOP condition, the address counter ‘wraps around,’

and previously transmitted data will be overwritten.

When all 16 bytes are received, and the STOP condition

has been sent by the Master, the internal programming cycle

begins. At this point, all received data is written to the

CAT1161/2 in a single write cycle.

Figure 7. Byte Write Timing

BYTE

ADDRESS

SLAVE

ADDRESS

DATA

BUS ACTIVITY:

MASTER

SDA LINE

Figure 8. Page Write Timing

BUS ACTIVITY:

MASTER

SDA LINE

DATA n+15

BYTE

ADDRESS (n)

DATA n

DATA n+1

SLAVE

ADDRESS

Acknowledge Polling

Disabling of the inputs can be used to take advantage of

the typical write cycle time. Once the stop condition is issued

to indicate the end of the host’s write operation, the

CAT1161/2 initiates the internal write cycle. ACK polling

can be initiated immediately. This involves issuing the start

condition followed by the slave address for a write

operation. If the CAT1161/2 is still busy with the write

operation, no ACK will be returned. If a write operation has

completed, an ACK will be returned and the host can then

proceed with the next read or write operation.

WRITE PROTECTION

The Write Protection feature allows the user to protect

against inadvertent memory array programming. If the WP

pin is tied to V

CC, the entire memory array is protected and

becomes read only. The CAT1161/2 will accept both slave

and byte addresses, but the memory location accessed is

protected from programming by the device’s failure to send

an acknowledge after the first byte of data is received.

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READ OPERATIONS

The READ operation for the CAT1161/2 is initiated in the

same manner as the write operation with one exception, that

R/W

bit is set to one. Three different READ operations are

possible: Immediate/Current Address READ,

Selective/Random READ and Sequential READ.

Immediate/Current Address Read

The CAT1161/2 address counter contains the address of

the last byte accessed, incremented by one. In other words,

if the last READ or WRITE access was to address N, the

READ immediately following would access data from

address N+1. For all devices, N=E=2047. The counter will

wrap around to Zero and continue to clock out valid data for

the 16K devices. After the CAT1161/2 receives its slave

address information (with the R/W

bit set to one), it issues

an acknowledge, then transmits the 8−bit byte requested.

The master device does not send an acknowledge, but will

generate a STOP condition.

Figure 9. Immediate Address Read Timing

SCL

SDA8TH BIT

STOPNO ACKDATA OUT

SLAVE

ADDRESS

DATA

BUS ACTIVITY:

MASTER

SDA LINE

Selective/Random Read

Selective/Random READ operations allow the Master

device to select at random any memory location for a READ

operation. The Master device first performs a ‘dummy’

write operation by sending the START condition, slave

address and byte addresses of the location it wishes to read.

After the CAT1161/2 acknowledges, the Master device

sends the START condition and the slave address again, this

time with the R/W bit set to one. The CAT1161/2 then

responds with its acknowledge and sends the 8−bit byte

requested. The master device does not send an acknowledge

but will generate a STOP condition.

Sequential Read

The Sequential READ operation can be initiated by either

the Immediate Address READ or Selective READ

operations. After the CAT1161/2 sends the inital 8−bit byte

requested, the Master will responds with an acknowledge

which tells the device it requires more data. The CAT1161/2

will continue to output an 8−bit byte for each acknowledge,

thus sending the STOP condition.

The data being transmitted from the CAT1161/2 is

outputted sequentially with data from address N followed by

data from address N+1. The READ operation address

counter increments all of the CAT1161/2 address bits so that

the entire memory array can be read during one operation.

If more than E (where E=2047 for the CAT1161/2) bytes are

read out, the counter will ‘wrap around’ and continue to

clock out data bytes.

Manual Reset Operation

The CAT116x RESET or RESET pin can also be used as

a manual reset input.

Only the “active” edge of the manual reset input is

internally sensed. The positive edge is sensed if RESET is

used as a manual reset input and the negative edge is sensed

if RESET

is used as a manual reset input.

An internal counter starts a 200 ms count. During this

time, the complementary reset output will be kept in the

active state. If the manual reset input is forced active for

more than 200 ms, the complementary reset output will

switch back to the non active state after the 200 ms expired,

regardless for how long the manual reset input is forced

active.

The embedded EEPROM is disabled as long as a reset

condition is maintained on any RESET pin. If the external

forced RESET/RESET

is longer than internal controlled

time−out period, t

PURST

, the memory will not respond with

an acknowledge for any access as long as the manual reset

input is active.

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CAT1162WI28

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Description:

Supervisory Circuits 16K I2C Mem w/Reset

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CAT1162WI28

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