UG-504 Evaluation Board User Guide
Rev. 0 | Page 4 of 12
A standard oscilloscope probe has a long wire ground clip. For
high frequency measurements, this ground clip picks up high
frequency noise and injects it into the measured output ripple.
Figure 2 shows an easy way to measure the output ripple properly.
It requires removing the oscilloscope probe sheath and wrapping
an unshielded wire around the oscilloscope probe. By keeping
the ground length of the oscilloscope probe as short as possible,
the true ripple can be measured.
11203-002
Figure 2. Measuring Output Voltage Ripple
MODIFYING THE BOARD
To modif y the ADP2380/ADP2381 evaluation board
configuration, unsolder and/or replace/remove the appropriate
passive components or jumpers on the board.
Changing the Output Voltages
The output voltage setpoints of the ADP2380 and the ADP2381
can be changed by replacing the R9 and R11 resistors with the
resistor values shown in Table 1.
Table 1. Resistive Divider for Various Output Voltages
V
OUT
(V) R9, ±1% (kΩ) R11, ±1% (kΩ)
1.0 10 15
1.2 10 10
1.5 15 10
1.8 20 10
2.5 47.5 15
3.3 10 2.21
5.0 22 3
To limit output voltage accuracy degradation due to the FB pin bias
current (0.1 μA maximum) to less than 0.5% (maximum), ensure
that the bottom divider string resistor, R11, is less than 30 kΩ.
The value of the top resistor, R9, is calculated using the following
equation:
R9 = R11 ×
0.6 V
0.6 V
OUT
V
When the output voltage is changed, the values of the inductor
(L1), the output capacitors (C2, C3, and C4), and the compensation
components (R8, C10, and C11) must be recalculated and changed
to ensure stable operation (see the ADP2380 and ADP2381 data
sheets for details on external component selection).
Changing the Switching Frequency
The switching frequency (f
SW
) set point can be changed by
replacing the R7 resistor with a different value, as shown in
the following equation:
f
SW
[kHz] = 57, 600/(R7 [kΩ] + 15)
A 215 kΩ resistor sets the frequency to 250 kHz, and a 100 kΩ
resistor sets the frequency to 500 kHz.
When the switching frequency is changed, the values of
the inductor (L1), the output capacitors (C2, C3, C4), and
the compensation networks (R8, C10, C11) must be recalculated
and changed for stable operation (see the ADP2380 and ADP2381
data sheets for details on external component selection).
Changing the Soft Start Time
The soft start time of the ADP2380/ADP2381 on the evaluation
board is programmed to 4 ms.
To change the soft start time, t
SS
, replace the C9 capacitor value,
using the following equation:
C9 [nF] = 5.5 × t
SS
[ms]
Changing the Input Voltage UVLO
The default values of PVIN UVLO rising/falling threshold are
4.2 V/3.9 V, and these default values can be replaced by placing
an external voltage divider (R4 and R6) to achieve more accurate,
externally adjustable UVLO. Lower values of the external resistors
are recommended to get high accuracy of the UVLO threshold.
Setting R6 to 1 kΩ is a proper choice, and the value of R4 for
a chosen input voltage rising threshold is as follows:
R4 =
V2.1
V)2.1(
_
R6V
RISINGIN
where:
V
IN_RISING
is the input voltage rising threshold. The input voltage
falling threshold can be determined by the following equation:
V
IN_FALLING
=
R6
R4V1.1
+ 1.1 V
External Synchronization
To synchronize the regulator to an external clock signal, apply
an external clock signal to J9 (SYNC) of the evaluation board.
The clock signal must have a logic high level from 1.3 V to 5 V
and a logic low level that is below 0.4 V. Set the external clock
pulse width to greater than 100 ns and the frequency range to
between 250 kHz and 1.4 MHz.
During synchronization, the regulator operates in CCM mode,
and the rising edge of the switching waveform runs 180° out of
phase to the external clock rising edge.
For reliable synchronization, connect a resistor from the RT pin
to GND (R7) to program the internal oscillator to run at 90% to
110% of the external synchronization clock signal.
