DocID008216 Rev 3 7/13
HCF4021 Electrical characteristics
13
Table 7. Dynamic electrical characteristics (T
amb
= 25 °C, C
L
= 50 pF, R
L
= 200 k, t
r
=
t
f
= 20 ns)
Symbol Parameter
Test condition Value
(1)
1. The typical temperature coefficient for all V
DD
values is 0.3 %/°C.
Unit
V
DD
(V) Min. Typ. Max.
t
PLH
, t
PHL
Propagation delay time
5 160 320
ns
10 80 160
15 60 120
t
THL
, t
TLH
Transition time
5 100 200
10 50 100
15 40 80
f
CL
(2)
2. If more than one unit is cascaded, t
r
CL should be made less than or equal to the sum of the transition time
and the fixed propagation delay of the output of the driving stage of the estimated capacitive load.
Maximum clock input frequency
536
MHz10 6 12
15 8.5 17
t
w
Clock pulse width
5 180 90
ns10 80 40
15 50 25
t
r
, t
f
Clock input rise or fall time
5
15 s10
15
t
s
Minimum setup time, serial input
t
H
200 ns
(ref to CL)
5 120 60
ns
10 80 40
15 60 30
Minimum setup time, parallel
inputs
t
H
200 ns
(ref to P/S)
55025
10 30 15
15 20 10
t
h
Hold time, serial in, parallel in,
parallel/serial control
5
010
15
t
WH
P/S pulse width
5 160 80
10 80 40
15 50 25
t
rem
P/S removal time
ref to CL)
5 280 140
10 140 70
15 100 50
Electrical characteristics HCF4021
8/13 DocID008216 Rev 3
Figure 4. Test circuit
1. Legend: C
L
= 50 pF or equivalent (includes jig and probe capacitance), R
L
= 200 KR
T
= Z
OUT
of pulse
generator (typically 50 )
Figure 5. Waveform 1: propagation delay times, clock pulse width
(f = 1 MHz; 50 % duty cycle)
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DocID008216 Rev 3 9/13
HCF4021 Electrical characteristics
13
Figure 6. Waveform 2: setup and hold times (SI to CLOCK)
(f = 1 MHz; 50 % duty cycle)
Figure 7. Waveform 3: setup and hold time (PI to P/S)
(f = 1 MHz; 50 % duty cycle)
Figure 8. Waveform 4: pulse width and removal time (P/S to clock)
(f = 1 MHz; 50 % duty cycle)
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HCF4021YM013TR

Mfr. #:
Manufacturer:
STMicroelectronics
Description:
Counter Shift Registers 8-Stage Static FlipFlop/registers
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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