AD8610/AD8620
Rev. F | Page 13 of 24
THEORY OF OPERATION
+
V
IN
2
0V p-
p
3
2
U1
+13V
–13V
R4
2k
R2
2k
R1
20k
R3
2k
U2
5
6
7
V+
V–
V–
V+
CS (dB) = 20 log (V
OUT
/ 10 × V
IN
)
0
2730-041
Figure 41. Channel Separation Test Circuit
FUNCTIONAL DESCRIPTION
The AD8610/AD8620 are manufactured on the Analog Devices,
Inc., XFCB (eXtra fast complementary bipolar) process. XFCB
is fully dielectrically isolated (DI) and used in conjunction with
N-channel JFET technology and thin film resistors (that can be
trimmed) to create the JFET input amplifier. Dielectrically isolated
NPN and PNP transistors fabricated on XFCB have an f
τ
> 3 GHz.
Low TC thin film resistors enable very accurate offset voltage and
offset voltage temperature coefficient trimming. These process
breakthroughs allow Analog Devices IC designers to create an
amplifier with faster slew rate and more than 50% higher band-
width at half of the current consumed by its closest competition.
The AD8610/AD8620 are unconditionally stable in all gains,
even with capacitive loads well in excess of 1 nF. The AD8610B
grade achieves less than 100 V of offset and 1 V/°C of offset
drift, numbers usually associated with very high precision bipolar
input amplifiers. The AD8610 is offered in the tiny 8-lead MSOP
as well as narrow 8-lead SOIC surface-mount packages and is
fully specified with supply voltages from ±5.0 V to ±13 V. The
very wide specified temperature range, up to 125°C, guarantees
superior operation in systems with little or no active cooling.
The unique input architecture of the AD8610/AD8620 features
extremely low input bias currents and very low input offset voltage.
Low power consumption minimizes the die temperature and
maintains the very low input bias current. Unlike many competi-
tive JFET amplifiers, the AD8610/AD8620 input bias currents are
low even at elevated temperatures. Typical bias currents are less
than 200 pA at 85°C. The gate current of a JFET doubles every
10°C, resulting in a similar increase in input bias current over
temperature. Give special care to the PC board layout to minimize
leakage currents between PCB traces. Improper layout and
board handling generates a leakage current that exceeds the bias
current of the AD8610/AD8620.
138
136
120
128
126
124
122
132
130
134
02730-042
CS (dB)
FREQUENCY (kHz)
0 100 150 20050 250 300 350
Figure 42. AD8620 Channel Separation Graph
Power Consumption
A major advantage of the AD8610/AD8620 in new designs is
the power saving capability. Lower power consumption of the
AD8610/AD8620 makes them much more attractive for portable
instrumentation and for high density systems, simplifying thermal
management, and reducing power-supply performance require-
ments. Compare the power consumption of the AD8610 vs. the
OPA627 in Figure 43.
8
7
2
6
5
4
3
02730-043
SUPPLY CURRENT (mA)
TEMPERATURE (°C)
–75 –25 0 25–50 50 75 100 125
OPA627
AD8610
Figure 43. Supply Current vs. Temperature
AD8610/AD8620
Rev. F | Page 14 of 24
Driving Large Capacitive Loads
The AD8610/AD8620 have excellent capacitive load driving
capability and can safely drive up to 10 nF when operating with
a ±5.0 V supply. Figure 44 and Figure 45 compare the AD8610/
AD8620 against the OPA627 in the noninverting gain configu-
ration driving a 10 k resistor and 10,000 pF capacitor placed
in parallel on its output, with a square wave input set to a frequency
of 200 kHz. The AD8610/AD8620 have much less ringing than
the OPA627 with heavy capacitive loads.
02730-044
VOLTAGE (20mV/DIV)
TIME (2µs/DIV)
V
S
= ±5V
R
L
= 10k
C
L
= 10,000pF
Figure 44. OPA627 Driving C
L
= 10,000 pF
02730-045
VOLTAGE (20mV/DIV)
TIME (2µs/DIV)
V
S
= ±5V
R
L
= 10k
C
L
= 10,000pF
Figure 45. AD8610/AD8620 Driving C
L
= 10,000 pF
The AD8610/AD8620 can drive much larger capacitances
without any external compensation. Although the AD8610/
AD8620 are stable with very large capacitive loads, remember
that this capacitive loading limits the bandwidth of the amplifier.
Heavy capacitive loads also increase the amount of overshoot
and ringing at the output. Figure 47 and Figure 48 show the
AD8610/AD8620 and the OPA627 in a noninverting gain of +2
driving 2 F of capacitance load. The ringing on the OPA627 is
much larger in magnitude and continues 10 times longer than
the AD8610/AD8620.
V
IN
= 50mV
2k 2k
–5V
+5
V
2µF
3
2
7
4
02730-046
Figure 46. Capacitive Load Drive Test Circuit
02730-047
VOLTAGE (50mV/DIV)
TIME (20µs/DIV)
V
S
= ±5V
R
L
= 10k
C
L
= 2µF
Figure 47. OPA627 Capacitive Load Drive, A
V
= +2
02730-048
VOLTAGE (50mV/DIV)
TIME (20µs/DIV)
V
S
= ±5V
R
L
= 10k
C
L
= 2µF
Figure 48. AD8610/AD8620 Capacitive Load Drive, A
V
= +2
AD8610/AD8620
Rev. F | Page 15 of 24
Slew Rate (Unity Gain Inverting vs. Noninverting)
Amplifiers generally have a faster slew rate in an inverting unity
gain configuration due to the absence of the differential input
capacitance. Figure 49 through Figure 52 show the performance
of the AD8610/AD8620 configured in a unity gain of –1 compared
to the OPA627. The AD8610/AD8620 slew rate is more symme-
trical, and both the positive and negative transitions are much
cleaner than in the OPA627.
02730-049
VOLTAGE (5V/DIV)
TIME (400ns/DIV)
V
S
= ±13V
R
L
= 2k
G=1
SR = 54Vs
Figure 49. +Slew Rate of AD8610/AD8620 in Unity Gain of –1
02730-050
VOLTAGE (5V/DIV)
TIME (400ns/DIV)
V
S
= ±13V
R
L
= 2k
G=1
SR = 42.1Vs
Figure 50. +Slew Rate of OPA627 in Unity Gain of –1
02730-051
VOLTAGE (5V/DIV)
TIME (400ns/DIV)
V
S
= ±13V
R
L
= 2k
G=1
SR = 54V/µs
Figure 51. –Slew Rate of AD8610/AD8620 in Unity Gain of –1
02730-052
VOLTAGE (5V/DIV)
TIME (400ns/DIV)
V
S
= ±13V
R
L
= 2k
G=1
SR = 56Vs
Figure 52. –Slew Rate of OPA627 in Unity Gain of –1
The AD8610/AD8620 have a very fast slew rate of 60 V/s even
when configured in a noninverting gain of +1. This is the toughest
condition to impose on any amplifier because the input common-
mode capacitance of the amplifier generally makes its SR appear
worse. The slew rate of an amplifier varies according to the voltage
difference between its two inputs. To observe the maximum SR,
a voltage difference of about 2 V between the inputs must be
ensured. This is required for virtually any JFET op amp so that
one side of the op amp input circuit is completely off, thus maxi-
mizing the current available to charge and discharge the internal
compensation capacitance. Lower differential drive voltages
produce lower slew rate readings. A JFET input op amp with a
slew rate of 60 V/s at unity gain with V
IN
= 10 V may slew at
20 V/s if it is operated at a gain of +100 with V
IN
= 100 mV.

AD8620ARZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Precision Amplifiers Low Inpt Bias Crnt WdeBW JFET Prec Dual
Lifecycle:
New from this manufacturer.
Delivery:
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