MAX769
2 or 3-Cell, Step-Up/Down,
Two-Way Pager System IC
______________________________________________________________________________________ 13
All DC-DC converter and charging circuitry is disabled
when the backup regulator is turned on, but all other
functions remain active. Activate BACKUP manually or by
serial command, or set it to trigger automatically via LBO.
Automatic Backup
Setting the LBO_Sets_BACKUP serial bit (Table 1) pro-
grams the IC so that when LBO goes low, the backup
regulator automatically turns on without instructions from
the microprocessor (µP). When the LBO_Sets_BACKUP
bit is 0, the backup regulator is turned on only by setting
the BACKUP bit. The BACKUP bit also overrides the
LBO_Sets_BACKUP bit. Figure 3 shows the logic for this
function.
If the main battery is depleted and the NiCd battery is
drained during backup, RSO goes low while the back-
up regulator is supplying OUT (if RSI is used to monitor
OUT or REG1). When RSO falls, the serial registers
reset to their POR states (with the DC-DC converter on
in Coast Mode and the backup regulator off, see
Tables 1, 2, and 3). This prevents the IC from getting
hung up with the DC-DC converter off when a new main
battery is inserted. This sequence is required because
if the MAX769 did not default to “DC-DC converter on”
when coming out of reset, the µP (still reset by RSO)
would not be able to provide the device with serial
instructions to turn on.
Serial Interface
The MAX769 has an SPI-compatible serial interface.
The serial-interface lines are Chip Select (CS), Serial
Clock (SCL), Serial Data In (SDI), and Serial Data Out
(SDO). Serial input data is arranged in 8-bit bytes. Most
bytes contain a 3-bit address pointer (R2, R1, R0)
along with 5 bits of input data (D4–D0). For common
operations such as selecting Run or Coast Mode, acti-
vating REG2 or REG3, or turning on DR1 or DR2, only
the 000 (R2, R1, R0) address register needs to be writ-
ten. The serial input data format for all MAX769 opera-
tions is outlined in Tables 1, 2, and 3.
15mA_CHG
1mA_CHG
TO
CHARGER
CONTROL
TO
BACKUP
REGULATOR
BACKUP
LBO_SETS_BACKUP
LBO
Figure 3. Logic for Charger Control and BACKUP and for
LBO_Sets_BACKUP Serial Input Bits
2.510 110
4.911 111
4.811 011
4.701 111
4.601 011
4.511 101
4.411 001
4.301 101
4.201 001
4.110 111
4.010 011
3.900 111
3.800 011
3.710 101
3.610 001
3.500 101
3.400 001
3.311 110
3.211 010
3.101 110
3.001 010
2.911 100
2.811 000
2.701 100
2.601 000
2.410 0
1.9
1.8
10
V
OUT
(V)
2.300
0
0
OV1
110
2.20
0
0
OV3
0 010
2.110 100
2.0
100
000
OV0OV2OV4
10 000
Table 5. V
OUT
Output Voltage
SERIAL-DATA BIT
MAX769
2 or 3-Cell, Step-Up/Down,
Two-Way Pager System IC
14 ______________________________________________________________________________________
Serial data is clocked in and out MSB first. Input data is
latched on the CLK rising edge, and output data is
shifted out on the CLK falling edge. When CS goes low,
DO immediately contains the MSB output bit (D7). D6 is
not clocked out until the falling clock edge that follows
the first rising clock edge after a Chip Select. See the
timing diagrams in Figures 4 and 5.
SPI writes and reads concurrently, so it may be neces-
sary to perform dummy writes in order to read output
data. Four output data bits (D7–D4, Table 4) are sent
from SDO each time a serial operation occurs.
When R2 = 0, R0 and R1 are address pointers.
However, when R2 = 1, the 7 remaining bits (R1, R0
and D4–D0) become DAC programming bits. This vio-
lation of programming etiquette (R1 and R0 are some-
times address bits and other times data bits) allows the
CH DAC to be loaded with only one write operation.
Writing all zeros to the CH DAC turns it, the CH0, CH1,
and CH2 comparators, and the NICD and BATT volt-
age-sensing resistors off to minimize current consump-
tion. This reduces current drain from OUT by about
30µA.
• • •
• • •
• • •
• • •
CS
SCLK
DIN
DOUT
t
CSH
t
CSS
t
CL
t
DS
t
DH
t
DV
t
CH
t
DO
t
TR
t
CSH
Figure 4. Detailed Serial-Interface Timing
CS
SCL
SCO D7 D6
R1R2 D4R0 D2D3 D0D1
D5 D4 0 0 0 0
SDI
Figure 5. CS, SCL, SDO, and SDI Serial Timing
MAX769
2 or 3-Cell, Step-Up/Down,
Two-Way Pager System IC
______________________________________________________________________________________ 15
Applications Information
Component Selection
The MAX769 requires minimal design calculation and is
optimized for the component values shown in Figure 2.
However, some flexibility in component selection is still
allowed, as described in the following text. A list of suit-
able components is provided in Table 6.
Inductor L1 is nominally 68µH, but values from 47µH to
100µH should be satisfactory. The inductor current rat-
ing should be 300mA or more if full output current
(80mA) is needed. If less output current is required, the
inductor current rating can be reduced proportionally
but should never be less than 150mA.
Inductor resistance should be minimized for best effi-
ciency, but since the MAX769 N-channel switch resis-
tance is typically 0.9, efficiency does not improve
significantly for coil resistances below 0.4.
Filter capacitors C1–C4 should be low-ESR types (tan-
talum or ceramic) for lowest ripple and best noise
rejection. The values shown in Figure 2 are optimized
for each output’s rated current. Lower required output
current allows smaller capacitance values.
Resistors at the LBI and RSIN inputs set the voltage at
which the LBO and RSO outputs trigger. The voltage
threshold for both LBI and RSI is 0.6V. The resistors
required to set a desired trip voltage, (Figure 2) V
TRIP
,
are calculated by:
R1 = R2[(V
TRIP(LBO)
/ 0.6) - 1]
R3 = R4[(V
TRIP(LBO)
/ 0.6) - 1]
To minimize battery drain, use large values for R2 and
R4 (>100k) in the above equations; 470k is a good
starting value.
See the
Low-Noise Analog Supply (REG2)
section for
information on selecting R
OFS
.
Since LBO and RSO are open-drain outputs, pull-up
resistors are usually required. Normally these will be
pulled up to REG1. 100kis recommended as a com-
promise between response time and current drain,
although other values can be used. Since LBI and RSO
are high (open circuit) during normal operation, current
normally does not flow in the pull-up resistors until a
low-battery or reset event occurs.
Logic Levels
Note that since the MAX769’s internal logic is powered
from REG1, the input logic levels at the digital inputs
(DR2IN, RUN, SYNC, CS, and SDI) as well as the logic
output level of SDO are governed by the voltage at
REG1. Logic-high inputs at these pins should not
exceed V
REG1
. Digital inputs should either be driven
from external logic (or a µP) powered from REG1, or by
open-drain logic devices that are pulled up to REG1.
Board Layout and Noise Reduction
The MAX769 makes every effort in its internal design to
minimize noise and EMI. Nevertheless, prudent layout
practices are still suggested for best performance.
Recommendations are as follows:
1) Keep trace lengths at L1, LX1, and LX2, as well as
at PGND, as short and wide as possible. Since LX1
and LX2 toggle between V
BATT
and V
OUT
at a fast
rate, minimizing the trace length serves to reduce
excess PC board area that might act as an antenna.
2) Place the filter capacitors at OUT, REG1, REG2,
and REG3 as close to their respective pins as pos-
sible (no more than 0.5mm away).
3) Consider using an inductor at L1. A shielded induc-
tor at L1 will minimize radiated noise, but may not
be essential. Toroids will also exhibit EMI perfor-
mance similar to that of shielded coils.
4) Keep the power components at the uppermost part
of the IC to minimize coupling to other parts of the
circuit. The LX1, LX2, OUT, and PGND pins are
located at the uppermost part of the IC to facilitate
PC board layout. Other pins in this area are digital
and are not affected by close proximity to switching
nodes.
5) Use a separate short, wide ground trace for PGND
and the ground side of the BATT and OUT filter
capacitors. Tie this trace to the ground plane.
Table 6. External Components
SUPPLIER PART NO. COMMENTS
CD54-680
LQH4N680K
1.9, 2.6mm high,
low current, low cost
Murata
Sumida
0.46, 4.5mm high
CDR74B-680
Coilcraft
DT1608C-223,
DT1608C-683
0.58, 3.18mm high,
shielded
AVX TPS series Tantalum
Marcon THCR series Ceramic
Sprague 595D series Tantalum
TDK C3216 series Ceramic
0.33, 4.5mm high,
shielded
CD73-680
0.33, 3.5mm high
Polystor A-10300 1.5 Farads
INDUCTORS (68µH)
CAPACITORS
STORAGE CAPACITOR (optional at NICD pin)

MAX769EEI+

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Power Management Specialized - PMIC 2-3 Cell Step-Up/Dwn 2-Way Pgr System IC
Lifecycle:
New from this manufacturer.
Delivery:
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