74F543PC

© 2000 Fairchild Semiconductor Corporation DS009554 www.fairchildsemi.com
April 1988
Revised October 2000
74F543 Octal Registered Transceiver
74F543
Octal Registered Transceiver
General Description
The F543 octal transceiver contains two sets of D-type
latches for temporary storage of data flowing in either
direction. Separate Latch Enable and Output Enable inputs
are provided for each register to permit independent con-
trol of inputting and outputting in either direction of data
flow. The A outputs are guaranteed to sink 24 mA while the
B outputs are rated for 64 mA.
Features
8-bit octal transceiver
Back-to-back registers for storage
Separate controls for data flow in each direction
A outputs sink 24 mA
B outputs sink 64 mA
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
IEEE/IEC
Connection Diagram
Order Number Package Number Package Description
74F543SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74F543MSA MSA24 24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
74F543PC N24A 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-011, 0.600 Wide
74F543SPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
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74F543
Unit Loading/Fan Out
Functional Description
The F543 contains two sets of eight D-type latches, with
separate input and output controls for each set. For data
flow from A to B, for example, the A-to-B Enable (CEAB
)
input must be LOW in order to enter data from A
0
A
7
or
take data from B
0
B
7
, as indicated in the Data I/O Control
Table. With CEAB
LOW, a LOW signal on the A-to-B Latch
Enable (LEAB
) input makes the A-to-B latches transparent;
a subsequent LOW-to-HIGH transition of the LEAB
signal
puts the A latches in the storage mode and their outputs no
longer change with the A inputs. With CEAB
and OEAB
both LOW, the 3-STATE B output buffers are active and
reflect the data present at the output of the A latches. Con-
trol of data flow from B to A is similar, but using the CEBA
,
LEBA
and OEBA inputs.
Data I/O Control Table
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
A-to-B data flow shown; B-to-A flow control is the same, except using
CEBA
, LEBA and OEBA
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Pin Names Description
U.L.
Input I
IH
/I
IL
HIGH/LOW
Output I
OH
/I
OL
OEAB A-to-B Output Enable Input (Active LOW) 1.0/1.0 20 µA/0.6 mA
OEBA
B-to-A Output Enable Input (Active LOW) 1.0/1.0 20 µA/0.6 mA
CEAB
A-to-B Enable Input (Active LOW) 1.0/2.0 20 µA/1.2 mA
CEBA
B-to-A Enable Input (Active LOW) 1.0/2.0 20 µA/1.2 mA
LEAB
A-to-B Latch Enable Input (Active LOW) 1.0/1.0 20 µA/0.6 mA
LEBA
B-to-A Latch Enable Input (Active LOW) 1.0/1.0 20 µA/0.6 mA
A
0
A
7
A-to-B Data Inputs or 3.5/1.083 70 µA/650 µA
B-to-A 3-STATE Outputs 150/40 (33.8)
3 mA/24 mA (20 mA)
B
0
B
7
B-to-A Data Inputs or 3.5/1.083 70 µA/650 µA
A-to-B 3-STATE Outputs 600/106.6 (80)
12 mA/64 mA (48 mA)
Inputs Latch Output
CEAB
LEAB OEAB Status Buffers
H X X Latched High Z
X H X Latched
L L X Transparent
XXH High Z
LXL Driving
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74F543
Absolute Maximum Ratings(Note 1) Recommended Operating
Conditions
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Storage Temperature 65°C to +150°C
Ambient Temperature under Bias
55°C to +125°C
Junction Temperature under Bias
55°C to +150°C
V
CC
Pin Potential to Ground Pin 0.5V to +7.0V
Input Voltage (Note 2)
0.5V to +7.0V
Input Current (Note 2)
30 mA to +5.0 mA
Voltage Applied to Output
in HIGH State (with V
CC
= 0V)
Standard Output
0.5V to V
CC
3-STATE Output 0.5V to +5.5V
Current Applied to Output
in LOW State (Max) twice the rated I
OL
(mA)
Free Air Ambient Temperature 0
°C to +70°C
Supply Voltage
+4.5V to +5.5V
Symbol Parameter Min Typ Max Units
V
CC
Conditions
V
IH
Input HIGH Voltage 2.0 V Recognized as a HIGH Signal
V
IL
Input LOW Voltage 0.8 V Recognized as a LOW Signal
V
CD
Input Clamp Diode Voltage 1.2 V Min I
IN
= 18 mA
V
OH
Output HIGH Voltage 10% V
CC
2.5 I
OH
= 1 mA (A
n
)
10% V
CC
2.4 I
OH
= 3 mA (A
n
, B
n
)
5% V
CC
2.7 V Min I
OH
= 1 mA (A
n
)
5% V
CC
2.7 I
OH
= 3 mA (A
n
, B
n
)
10% V
CC
2.0 I
OH
= 15 mA (B
n
)
V
OL
Output LOW 10% V
CC
0.5 V Min I
OL
= 24 mA (A
n
)
Voltage 10% V
CC
0.55 I
OL
= 64 mA (B
n
)
I
IH
Input HIGH Current 5.0 µAMaxV
IN
= 2.7V
I
BVI
Input HIGH Current
7.0 µAMax
(OEAB, OEBA, LEAB,
Breakdown Test LEBA, CEAB, CEBA)
I
BVIT
Input HIGH Current
0.5 mA Max V
IN
= 5.5V (A
n
, B
n
)
Breakdown (I/O)
I
CEX
Output HIGH
50 µAMaxV
OUT
= V
CC
Leakage Current
V
ID
Input Leakage
4.75 V 0.0
I
ID
= 1.9 µA
Test All Other Pins Grounded
I
OD
Output Leakage
3.75 µA0.0
V
IOD
= 150 mV
Circuit Current All Other Pins Grounded
I
IL
Input LOW Current 0.6
mA Max
V
IN
= 0.5V (OEAB, OEBA)
1.2 V
IN
= 0.5V (CEAB, CEBA)
I
IH
+ I
OZH
Output Leakage Current 70 µAMaxV
OUT
= 2.7V (A
n
, B
n
)
I
IL
+ I
OZL
Output Leakage Current 650 µAMaxV
OUT
= 0.5V (A
n
, B
n
)
I
OS
Output Short-Circuit Current 60 150
mA Max
V
OUT
= 0V (A
n
)
100 225 V
OUT
= 0V (B
n
)
I
ZZ
Bus Drainage Test 500 µA0.0VV
OUT
= 5.25V (A
n
, B
n
)
I
CCH
Power Supply Current 67 100 mA Max V
O
= HIGH
I
CCL
Power Supply Current 83 125 mA Max V
O
= LOW
I
CCZ
Power Supply Current 83 125 mA Max V
O
= HIGH Z

74F543PC

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
IC TXRX NON-INVERT 5.5V 24DIP
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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