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MAX127ACNG+

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
MAX127/MAX128
Multirange, +5V, 12-Bit DAS with
2-Wire Serial Interface
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= +5V ±5%; unipolar/bipolar range; external reference mode, V
REF
= 4.096V; 4.7µF at REF pin; external clock, f
CLK
= 400kHz;
T
A
= T
MIN
to T
MAX
; unless otherwise noted. Typical values are at T
A
= +25°C.)
V2.4 4.18Input Voltage Range
VV
DD
- 0.5
REFADJ Threshold for
Buffer Disable
Normal or STANDBY power-down mode kΩ10
Input Resistance
FULL power-down mode 5 MΩ
External reference = 4.096V
CONDITIONS
FULL power-down mode
LSB
±0.1 ±0.5
PSRR
Power-Supply Rejection Ratio
(Note 7)
µs
V4.75 5.25V
DD
Supply Voltage
6.0 7.7 10.0t
CONV
Conversion Time
120 220
Normal mode, bipolar ranges
700 850
Normal mode, unipolar ranges
UNITSMIN TYP MAXSYMBOLPARAMETER
STANDBY power-down mode (Note 6)
mA
18
I
DD
Supply Current
6 10
µA
Internal reference ±0.5
0.4f
CLK
External Clock Frequency Range MHz
Power-up (Note 8) µs200
Bandgap Reference
Start-Up Time
ksps8Throughput Rate
C
IN
15 pF(Note 4)
Input Leakage Current I
IN
±0.1 ±10 µAV
IN
= 0 or V
DD
Input Low Threshold Voltage V
IL
0.8 V
Input High Threshold Voltage V
IH
2.4 V
Input Capacitance
V
HYS
0.2 VInput Hysteresis
400
V
REF
=
4.18V
µA
1
Input Current
FULL power-down mode
Normal, or STANDBY
power-down mode
To 0.1mV, REF bypass
capacitor fully discharged
ms
8
Reference Buffer Settling Time
POWER REQUIREMENTS
TIMING
REFERENCE INPUT (buffer disabled, reference input applied to REF)
DIGITAL INPUTS (SHDN, A2, A1, A0)
C
REF
= 4.7µF
C
REF
= 33µF 60
MAX127/MAX128
Multirange, +5V, 12-Bit DAS with
2-Wire Serial Interface
_______________________________________________________________________________________ 5
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= +5V ±5%; unipolar/bipolar range; external reference mode, V
REF
= 4.096V; 4.7µF at REF pin; external clock, f
CLK
= 400kHz;
T
A
= T
MIN
to T
MAX
; unless otherwise noted. Typical values are at T
A
= +25°C.)
Input Hysteresis V
HYS
0.05 x V
DD
V
Input Low Threshold Voltage V
IL
0.3 x V
DD
V
Input High Threshold Voltage V
IH
0.7 x V
DD
V
PARAMETER SYMBOL MIN TYP MAX UNITSCONDITIONS
TIMING CHARACTERISTICS
(V
DD
= +4.75V to +5.25V; unipolar/bipolar range; external reference mode, V
REF
= 4.096V; 4.7µF at REF pin; T
A
= T
MIN
to T
MAX
;
unless otherwise noted. Typical values are at T
A
= +25°C.)
Input Capacitance C
IN
15 pF(Note 4)
Input Leakage Current I
IN
±0.1 ±10 µAV
IN
= 0 or V
DD
Three-State Output Capacitance C
OUT
15 pF(Note 4)
Output Low Voltage V
OL
0.4
V
I
SINK
= 3mA
2-WIRE FAST MODE
Hold Time (Repeated)
START Condition
t
HD,STA
0.6 µs
Bus Free Time Between a
STOP and START Condition
t
BUF
1.3 µs
SCL Clock Frequency f
SCL
400 kHz
PARAMETERS SYMBOL MIN TYP MAX UNITSCONDITIONS
Set-Up Time for a Repeated
START Condition
t
SU,STA
0.6 µs
High Period of the SCL Clock t
HIGH
0.6 µs
Low Period of the SCL Clock t
LOW
1.3 µs
Rise Time for Both SDA and SCL
Signals (Receiving)
t
R
20 + 300
0.1 x C
b
nsC
b
= Total capacitance of one bus line in pF
Data Setup Time t
SU,DAT
100 ns
Data Hold Time t
HD,DAT
0 0.9 µs
DIGITAL INPUTS (SDA, SCL)
DIGITAL OUTPUTS (SDA)
I
SINK
= 6mA 0.6
Fall Time for Both SDA and SCL
Signals (Receiving)
t
F
C
b
= Total capacitance of one bus line in pF
20 + 300
0.1 x C
b
ns
Fall Time for Both SDA and SCL
Signals (Transmitting)
t
F
C
b
= Total capacitance of one bus line in pF
20 + 250
0.1 x C
b
ns
Set-Up Time for STOP Condition t
SU,STO
0.6 µs
Capacitive Load for Each
Bus Line
C
b
400 pF
Pulse Width of Spike Suppressed t
SP
0 50 ns
2-WIRE FAST MODE
MAX127/MAX128
Multirange, +5V, 12-Bit DAS with
2-Wire Serial Interface
6 _______________________________________________________________________________________
TIMING CHARACTERISTICS (continued)
(V
DD
= +4.75V to +5.25V; unipolar/bipolar range; external reference mode, V
REF
= 4.096V; 4.7µF at REF pin; T
A
= T
MIN
to T
MAX;
unless otherwise noted. Typical values are at T
A
= +25°C.)
Note 1: Accuracy specifications tested at V
DD
= 5.0V. Performance at power-supply tolerance limits is guaranteed by Power-
Supply Rejection test.
Note 2: External reference: V
REF
= 4.096V, offset error nulled, ideal last-code transition = FS - 3/2LSB.
Note 3: Ground “on” channel, sine wave applied to all “off” channels.
Note 4: Guaranteed by design. Not tested.
Note 5: Use static external load during conversion for specified accuracy.
Note 6: Tested using internal reference.
Note 7: PSRR measured at full scale. Tested for the ±10V (MAX127) and ±4.096V (MAX128) input ranges.
Note 8: Not subject to production testing. Provided for design guidance only.
PARAMETERS SYMBOL MIN TYP MAX UNITSCONDITIONS
Low Period of the SCL Clock t
LOW
4.7 µs
High Period of the SCL Clock t
HIGH
4.0 µs
Setup Time for a Repeated
START Condition
t
SU, STA
4.7 µs
Data Hold Time t
HD, DAT
0 0.9 µs
Data Setup Time t
SU, DAT
250 ns
Rise Time for Both SDA and SCL
Signals (Receiving)
t
R
1000 ns
Fall Time for Both SDA and SCL
Signals (Receiving)
t
F
300 ns
Fall Time for Both SDA and SCL
Signals (Transmitting)
t
F
C
b
= total capacitance of one bus line in pF,
up to 6mA sink
20 + 250
0.1 x C
b
ns
Setup Time for STOP Condition t
SU, STO
4.0 µs
Capacitive Load for Each
Bus Line
C
b
400 pF
Pulse Width of Spike Suppressed t
SP
0 50 ns
Hold Time (Repeated) START
Condition
t
HD,STA
4.0 µs
Bus Free Time Between a STOP
and START Condition
t
BUF
4.7 µs
SCL Clock Frequency f
SCL
100 kHz
2-WIRE STANDARD MODE
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

MAX127ACNG+

Mfr. #:
Buy MAX127ACNG+
Manufacturer:
Maxim Integrated
Description:
Data Acquisition ADCs/DACs - Specialized 12-Bit 8Ch 8ksps 4.18V Precision ADC
Lifecycle:
New from this manufacturer.
Delivery:
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