X9259
13
FN8169.6
December 12, 2014
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DC Electrical Specifications Over the recommended operating conditions unless otherwise specified.
SYMBOL PARAMETER TEST CONDITIONS
LIMITS
MIN TYP MAX UNITS
I
CC1
V
CC
supply current
(active)
f
SCL
= 400kHz; V
CC
= +6V;
SDA = Open; (for 2-Wire, Active, Read and
Volatile Write States only)
3mA
I
CC2
V
CC
supply current
(nonvolatile write)
f
SCL
= 400kHz; V
CC
= +6V;
SDA = Open; (for 2-Wire, Active,
Nonvolatile Write State only)
5mA
I
SB
V
CC
current (standby) V
CC
= +6V; V
IN
= V
SS
or V
CC
; SDA = V
CC
;
(for 2-Wire, Standby State only)
A
I
LI
Input leakage current V
IN
= V
SS
to V
CC
10 µA
I
LO
Output leakage current V
OUT
= V
SS
to V
CC
10 µA
V
IH
Input HIGH voltage V
CC
x 0.7 V
V
IL
Input LOW voltage V
CC
x 0.3 V
V
OL
Output LOW voltage I
OL
= 3mA 0.4 V
V
OH
Output HIGH voltage I
OH
= -1mA, V
CC
+3V V
CC
- 0.8 V
V
OH
Output HIGH voltage I
OH
= -0.4mA, V
CC
+3V V
CC
- 0.4 V
Endurance and Data Retention
PARAMETER MIN UNITS
Minimum endurance 100,000 Data changes per bit per register
Data retention 100 years
Capacitance
SYMBOL TEST MAX UNITS TEST CONDITIONS
C
IN/OUT
(Note 15) Input / Output capacitance (SDA) 8 pF V
OUT
= 0V
C
IN
(Note 15) Input capacitance (SCL, WP, A2, A1 and A0) 6 pF V
IN
= 0V
Power-up Timing
SYMBOL PARAMETER MIN MAX UNITS
tr VCC
(Note 15)V
CC
Power-up rate 0.2 V/ms
tPUR
(Note 16) Power-up to initiation of read operation 1 ms
tPUW
(Note 16) Power-up to initiation of write operation 50 ms
AC Test Conditions
Input Pulse Levels V
CC
x 0.1 to V
CC
x 0.9
Input rise and fall times 10ns
Input and output timing level V
CC
x 0.5
NOTES:
15. This parameter is not 100% tested
16. t
PUR
and t
PUW
are the delays required from the time the power supply (V
CC
) is stable until the specific instruction can be issued. These parameters
are periodically sampled and not 100% tested.
X9259
14
FN8169.6
December 12, 2014
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Equivalent AC Load Circuit
5V
1533Ω
100pF
SDA pin
R
H
10pF
C
L
C
L
R
W
R
TOTAL
C
W
25pF
10pF
R
L
SPICE Macromodel
AC Timing
SYMBOL PARAMETER MIN MAX UNITS
f
SCL
Clock Frequency 400 kHz
t
CYC
Clock Cycle Time 2500 ns
t
HIGH
Clock High Time 600 ns
t
LOW
Clock Low Time 1300 ns
t
SU:STA
Start Setup Time 600 ns
t
HD:STA
Start Hold Time 600 ns
t
SU:STO
Stop Setup Time 600 ns
t
SU:DAT
SDA Data Input Setup Time 100 ns
t
HD:DAT
SDA Data Input Hold Time 30 ns
t
R
SCL and SDA Rise Time 300 ns
t
F
SCL and SDA Fall Time 300 ns
t
AA
SCL Low to SDA Data Output Valid Time 0.9 µs
t
DH
SDA Data Output Hold Time 0 ns
T
I
Noise Suppression Time Constant at SCL and SDA inputs 50 ns
t
BUF
Bus Free Time (Prior to Any Transmission) 1200 ns
t
SU:WPA
A0, A1 Setup Time 0 ns
t
HD:WPA
A0, A1 Hold Time 0 ns
High-Voltage Write Cycle Timing
SYMBOL PARAMETER TYP MAX UNITS
t
WR
High-voltage write cycle time (store instructions) 5 10 ms
XDCP Timing
SYMBOL PARAMETER MIN MAX UNITS
t
WRPO
Wiper response time after the third (last) power supply is stable 5 10 µs
t
WRL
Wiper response time after instruction issued (all load instructions) 5 10 µs
X9259
15
FN8169.6
December 12, 2014
Submit Document Feedback
Symbol Table
.
Timing Diagrams
Start and Stop Timing
Input Timing
Output Timing
WAVEFORM INPUTS OUTPUTS
Must be
steady
Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A Center Line
is High
Impedance
t
SU:STA
t
HD:STA
t
SU:STO
SCL
SDA
t
R
(START) (STOP)
t
F
t
R
t
F
SCL
SDA
t
HIGH
t
LOW
t
CYC
t
HD:DAT
t
SU:DAT
t
BUF
SCL
SDA
t
DH
t
AA

X9259UV24IZ-2.7T1

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Digital Potentiometer ICs QD DCP 50KOHM 256 TAPS 2-WIRE
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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