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X9259UV24IZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
X9259
4
FN8169.6
December 12, 2014
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Functional Pin Descriptions
Bus Interface Pins
SERIAL DATA INPUT/OUTPUT (SDA)
The SDA is a bidirectional serial data input/output pin for a
2-wire slave device and is used to transfer data into and out of
the device. It receives device address, opcode, wiper register
address and data sent from a 2-wire master at the rising edge of
the serial clock SCL, and it shifts out data after each falling edge
of the serial clock SCL.
It is an open-drain output and may be wire-ORed with any
number of open drain or open collector outputs. An open-drain
output requires the use of a pull-up resistor.
SERIAL CLOCK (SCL)
This input is used by a 2-wire master to supply a 2-wire serial
clock to the X9259.
DEVICE ADDRESS (A3 THROUGH A0)
The Address inputs are used to set the least significant 4 bits of
the 8-bit slave address. A match in the slave address serial data
stream must be made with the address input in order to initiate
communication with the X9259. A maximum of 16 devices may
occupy the 2-wire serial bus. Device pins A3 through A0 must be
tied to a logic level, which specifies the external address of the
device, see Figures 3
, 4, and 5.
Potentiometer Pins
R
H
, R
L
The R
H
and R
L
pins are equivalent to the terminal connections on
a mechanical potentiometer. Since there are 4 potentiometers,
there are 4 sets of R
H
and R
L
such that R
H0
and R
L0
are the
terminals of DCP0 and so on.
R
W
The wiper pin are equivalent to the wiper terminal of a
mechanical potentiometer. Since there are 4 potentiometers,
there are 4 sets of R
W
such that R
W0
is the terminal of DCP0 and
so on.
Bias Supply Pins
SYSTEM SUPPLY VOLTAGE (V
CC
) AND SUPPLY
GROUND (V
SS
)
The V
CC
pin is the system supply voltage. The V
SS
pin is the
system ground.
Other Pins
NO CONNECT
No connect pins should be left open. These pins are used for
Intersil manufacturing and testing purposes.
HARDWARE WRITE PROTECT INPUT (WP)
The WP pin when LOW, prevents nonvolatile writes to the Data
Registers.
SERIAL DATA PATH
FROM INTERFACE
CIRCUITRY
DR#0
SERIAL
BUS
INPUT
PARALLEL
BUS
INPUT
COUNTER
REGISTER
INC/DEC
LOGIC
UP/DN
CLK
MODIFIED SCK
UP/DN
8 8
COUNTER
IF WCR = 00[H] then R
W
is closest to R
L
IF WCR = FF[H] then R
W
is closest to R
H
WIPER
(WCR#)
#: 0, 1, 2, or 3
One of Four Potentiometers
DR#2
DR#1
DR#3
- - -
DECODE
DCP
CORE
R
W
R
H
R
L
FIGURE 1. DETAILED POTENTIOMETER BLOCK DIAGRAM
X9259
5
FN8169.6
December 12, 2014
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Principles of Operation
The X9259 is an integrated circuit incorporating four DCPs and
their associated registers and counters, and the serial interface
providing direct communication between a host and the
potentiometers.
DCP Description
Each DCP is implemented with a combination of resistor
elements and CMOS switches. The physical ends of each DCP are
equivalent to the fixed terminals of a mechanical potentiometer
(R
H
and R
L
pins). The RW pin is an intermediate node, equivalent
to the wiper terminal of a mechanical potentiometer.
The position of the wiper terminal within the DCP is controlled by
an 8-bit volatile Wiper Counter Register (WCR).
Power Up and Down Recommendations
There are no restrictions on the power-up or power-down
conditions of V
CC
and the voltages applied to the potentiometer
pins provided that V
CC
is always more positive than or equal to
V
H
, V
L
, and V
W
, i.e., V
CC
V
H
, V
L
, V
W
. The V
CC
ramp rate
specification is always in effect.
Wiper Counter Register (WCR)
The X9259 contains four Wiper Counter Registers, one for each
potentiometer. The Wiper Counter Register can be envisioned as
a 8-bit parallel and serial load counter with its outputs decoded
to select one of 256 wiper positions along its resistor array. The
contents of the WCR can be altered in four ways: it may be
written directly by the host via the Write Wiper Counter Register
instruction (serial load); it may be written indirectly by
transferring the contents of one of four associated data registers
via the XFR Data Register instruction (parallel load); it can be
modified one step at a time by the Increment/Decrement
instruction (see “
Instructions” section on page 8 for more
details). Finally, it is loaded with the contents of its data register
zero (DR#0) upon power-up, (see Figure 1 on page 4).
The Wiper Counter Register is a volatile register; that is, its
contents are lost when the X9259 is powered-down. Although the
register is automatically loaded with the value in DR#0 upon
power-up, this may be different from the value present at
power-down. Power-up guidelines are recommended to ensure
proper loadings of the DR#0 value into the WCR# (see AN162
).
Data Registers (DR)
Each of the four DCPs has four 8-bit nonvolatile Data Registers.
These can be read or written directly by the host. Data can also
be transferred between any of the four data registers and the
associated Wiper Counter Register. All operations changing data
in one of the data registers is a nonvolatile operation and takes a
maximum of 10ms.
If the application does not require storage of multiple settings for
the potentiometer, the Data Registers can be used as regular
memory locations for system parameters or user preference
data.
Bit [7:0] are used to store one of the 256 wiper positions
(0 ~ 255).
TABLE 1. WIPER COUNTER REGISTER, WCR (8-BIT), WCR[7:0]: USED TO STORE THE CURRENT WIPER POSITION (VOLATILE).
WCR7 WCR6 WCR5 WCR4 WCR3 WCR2 WCR1 WCR0
(MSB) (LSB)
TABLE 2. DATA REGISTER, DR (8-BIT), BIT [7:0]: USED TO STORE WIPER POSITIONS OR DATA (NONVOLATILE).
BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0
(MSB) (LSB)
X9259
6
FN8169.6
December 12, 2014
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Serial Interface
The X9259 supports a bidirectional bus oriented protocol. The
protocol defines any device that sends data onto the bus as a
transmitter and the receiving device as the receiver. The device
controlling the transfer is a master and the device being
controlled is the slave. The master always initiates data transfers
and provide the clock for both transmit and receive operations.
Therefore, the X9259 operates as a slave device in all
applications.
All 2-wire interface operations must begin with a START, followed
by an Identification Byte, that selects the X9259. All
communication over the 2-wire interface is conducted by sending
the MSB of each byte of data first.
Clock and Data Conventions
Data states on the SDA line can change only during SCL LOW
periods. SDA state changes during SCL HIGH are reserved for
indicating START and STOP conditions (see Figure 2
). On
power-up of the X9259, the SDA pin is in the input mode.
START Condition
All commands to the X9259 are preceded by the start condition,
which is a HIGH to LOW transition of SDA while SCL is HIGH. The
X9259 continuously monitors the SDA and SCL lines for the
START condition and does not respond to any command until this
condition is met (see Figure 2
).
STOP Condition
All communications must be terminated by a STOP condition,
which is a LOW to HIGH transition of SDA while SCL is HIGH, (see
Figure 2). The STOP condition is also used to place the device
into the Standby Power mode after a Read sequence. A STOP
condition can only be issued after the transmitting device has
released the bus.
Acknowledge
An ACK, Acknowledge, is a software convention used to indicate
a successful data transfer. The transmitting device, either master
or slave, releases the SDA bus after transmitting eight bits.
During the ninth clock cycle, the receiver pulls the SDA line LOW
to acknowledge the reception of the eight bits of data, (see
Figure 3
).
The X9259 responds with an ACK after recognition of a START
condition followed by a valid Identification Byte, and once again
after successful receipt of an Instruction Byte. The X9259 also
responds with an ACK after receiving a Data Byte after a Write
Instruction.
A valid Identification Byte contains the Device Type Identifier
0101, as the four MSBs, and the Device Address bits matching
the logic states of pins A3, A2, A1, and A0, as the four LSBs (see
Figure 4 on page 8
).
In the Read mode, the device transmits eight bits of data,
releases the SDA line, and then monitors the line for an ACK. The
device continues transmitting data if an ACK is detected. The
device terminates further data transmissions if an ACK is not
detected. The master must then issue a STOP condition to place
the device into a known state.
During the internal nonvolatile Write operation, the X9259
ignores the inputs at SDA and SCL, and does not issue an ACK
after Identification bytes.
FIGURE 2. VALID DATA CHANGES, START, AND STOP CONDITIONS
FIGURE 3. ACKNOWLEDGE RESPONSE FROM RECEIVER
SDA
SCL
START DATA DATA STOP
STABLE CHANGE
DATA
STABLE
SDA OUTPUT FROM
TRANSMITTER
SDA OUTPUT FROM
RECEIVER
81 9
START ACK
SCL FROM
MASTER
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

X9259UV24IZ

Mfr. #:
Buy X9259UV24IZ
Manufacturer:
Renesas / Intersil
Description:
Digital Potentiometer ICs QD DCP 50KOHM 256 TAPS 2-WIRE
Lifecycle:
New from this manufacturer.
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