X9259
7
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Identification Byte
The first byte sent to the X9259 from the host is called the
Identification Byte. The most significant four bits are a Device
Type Identifier, ID[3:0] bits, which must be 0101. Refer to
Table 3
.
Only the device which Slave Address matches the incoming
device address sent by the master executes the instruction. The
A3 - A0 inputs can be actively driven by CMOS input signals or
tied to V
CC
or V
SS
.
INSTRUCTION BYTE (I)
The next byte sent to the X9259 contains the instruction and
register pointer information. The four most significant bits are
used provide the instruction opcode I [3:0]. The RB and RA bits
point to one of the four data registers of each associated XDCP.
The least two significant bits point to one of four Wiper Counter
Registers or DCPs. The format is shown in Table 4
.
The least significant four bits of the Identification Byte are the
Slave Address bits, AD[3:0]. To access the X9259, these four bits
must match the logic values of pins A3, A2, A1, and A0.
Data Register Selection
REGISTER RB RA
DR#0 0 0
DR#1 0 1
DR#2 1 0
DR#3 1 1
#: 0, 1, 2, or 3
TABLE 3. IDENTIFICATION BYTE FORMAT
DEVICE TYPE IDENTIFIER SLAVE ADDRESS
ID3 ID2 ID1 ID0 A3 A2 A1 A0
0101 Logic value of pins A3, A2, A1, and A0
(MSB) (LSB)
TABLE 4. INSTRUCTION BYTE FORMAT
INSTRUCTION OPCODE REGISTER SELECTION
DCP SELECTION
(WCR SELECTION)
I3 I2 I1 I0 RB RA P1 P0
(MSB) (LSB)
TABLE 5. INSTRUCTION SET
INSTRUCTION
INSTRUCTION SET
OPERATIONI3 I2 I1 I0 RB RA P1 P0
Read Wiper Counter
Register
1 0 0 1 0 0 1/0 1/0 Read the contents of the Wiper Counter Register pointed
to by P1 - P0
Write Wiper Counter Register 1 0 1 0 0 0 1/0 1/0 Write new value to the Wiper Counter
Register pointed to by P1 - P0
Read Data Register 1 0 1 1 1/0 1/0 1/0 1/0 Read the contents of the Data Register pointed to by
P1 - P0 and RB - RA
Write Data Register 1 1 0 0 1/0 1/0 1/0 1/0 Write new value to the Data Register
pointed to by P1 - P0 and RB - RA
XFR Data Register to Wiper Counter
Register
1 1 0 1 1/0 1/0 1/0 1/0 Transfer the contents of the Data Register pointed to by
P1 - P0 and RB - RA to its
associated Wiper Counter Register
XFR Wiper Counter Register to Data
Register
1 1 1 0 1/0 1/0 1/0 1/0 Transfer the contents of the Wiper Counter Register
pointed to by P1 - P0 to the Data Register pointed to by
RB - RA
Global XFR Data Registers to Wiper
Counter Registers
0 0 0 1 1/0 1/0 0 0 Transfer the contents of the Data Registers pointed to by
RB - RA of all four pots to their respective Wiper Counter
Registers
Global XFR Wiper Counter Registers
to Data Register
1 0 0 0 1/0 1/0 0 0 Transfer the contents of both Wiper Counter Registers to
their respective data Registers pointed to by RB - RA of
all four DCPs
Increment/Decrement Wiper Counter
Register
0 0 1 0 0 0 1/0 1/0 Enable Increment/decrement of the Control Latch
pointed to by P1 - P0
NOTE: 1/0 = data is one or zero
X9259
8
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December 12, 2014
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Instructions
Four of the nine instructions are three bytes in length. These
instructions are:
Read Wiper Counter Register – read the current wiper position
of the selected potentiometer.
Write Wiper Counter Register – change current wiper position
of the selected potentiometer.
Read Data Register – read the contents of the selected Data
Register.
Write Data Register – write a new value to the selected Data
Register.
The basic sequence of the three byte instructions is illustrated in
Figure 5
. These three-byte instructions exchange data between
the WCR and one of the Data Registers. A transfer from a Data
Register to a WCR is essentially a write to a static RAM, with the
static RAM controlling the wiper position. The response of the
wiper to this action is delayed by t
WRL
. A transfer from the WCR
(current wiper position), to a Data Register is a write to
nonvolatile memory and takes a minimum of t
WR
to complete.
The transfer can occur between one of the four potentiometer’s
WCR, and one of its associated registers, DRs; or it may occur
globally, where the transfer occurs between all potentiometers
and one associated register.
Four instructions require a two-byte sequence to complete. These
instructions transfer data between the host and the X9259;
either between the host and one of the data registers or directly
between the host and the Wiper Counter Register. These
instructions are:
XFR Data Register to Wiper Counter Register – This transfers
the contents of one specified Data Register to the associated
Wiper Counter Register.
XFR Wiper Counter Register to Data Register – This transfers
the contents of the specified Wiper Counter Register to the
specified associated Data Register.
Global XFR Data Register to Wiper Counter
Register – This transfers the contents of all specified Data
Registers to the associated Wiper Counter Registers.
Global XFR Wiper Counter Register to Data
Register – This transfers the contents of all Wiper Counter
Registers to the specified associated Data Registers.
Increment/Decrement Command
The final command is Increment/Decrement (Figures 6 and 7).
The Increment/Decrement command is different from the other
commands. Once the command is issued and the X9259 has
responded with an Acknowledge, the master can clock the
selected wiper up and/or down in one segment steps; thereby,
providing a fine tuning capability to the host. For each SCL clock
pulse (t
HIGH
) while SDA is HIGH, the selected wiper moves one
wiper position towards the R
H
terminal. Similarly, for each SCL
clock pulse while SDA is LOW, the selected wiper moves one
resistor wiper position towards the R
L
terminal.
See
Instruction Format” on page 10 for more details.
FIGURE 4. TWO-BYTE INSTRUCTION SEQUENCE
FIGURE 5. THREE-BYTE INSTRUCTION SEQUENCE 2-WIRE INTERFACE
S
T
A
R
T
0101
A2 A0
A
C
K
I2 I1
I0
RB RA P1
A
C
K
SCL
SDA
S
T
O
P
ID3 ID2 ID1 ID0
P0
Device ID
External
Instruction
Opcode
Address
Register
Address
DCP/WCR
Address
A1
A3
I3
I3
I2
I1
I0
RB RA
ID3 ID2
ID1
ID0
Device ID
External
Instruction
Opcode
Address
Register
Address
Pot/WCR
Address
Data for WCR[7:0] or DR[7:0]
S
T
A
R
T
0 101
A2 A1 A0
A
C
K
P1 P0 A
C
K
SCL
SDA
S
T
O
P
A
C
K
D7 D6 D5 D4 D3 D2 D1 D0
A3
X9259
9
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December 12, 2014
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FIGURE 6. INCREMENT/DECREMENT INSTRUCTION SEQUENCE 2-WIRE INTERFACE
FIGURE 7. INCREMENT/DECREMENT TIMING SPECIFICATION
I3 I2
I1
I0
ID3 ID2 ID1 ID0
Device ID
External
Instruction
Opcode
Address
Register
Address
Pot/WCR
Address
S
T
A
R
T
0101
A2 A1 A0
A
C
K
RA P1 P0
A
C
K
SCL
SDA
S
T
O
P
I
N
C
1
I
N
C
2
I
N
C
n
D
E
C
1
D
E
C
n
RB
A3
SCL
SDA
R
W
INC/DEC
CMD
ISSUED
VOLTAGE OUT
t
WRID

X9259UV24IZT1

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Digital Potentiometer ICs QD DCP 50KOHM 256 TAPS 2-WIRE TR 24LD
Lifecycle:
New from this manufacturer.
Delivery:
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