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MM74HC221A
Theory of Operation
FIGURE 1.
TRIGGER OPERATION
As shown in Figure 1 and the logic diagram before an input
trigger occurs, the monostable is in the quiescent state with
the Q output LOW, and the timing capacitor C
EXT
com-
pletely charged to V
CC
. When the trigger input A goes from
V
CC
to GND (while inputs B and clear are held to V
CC
) a
valid trigger is recognized, which turns on comparator C1
and N-channel transistor N11. At the same time the output
latch is set. With transistor N1 on, the capacitor C
EXT
rap-
idly discharges toward GND until V
REF1
is reached. At this
point the output of comparator C1 changes state and tran-
sistor N1 turns off. Comparator C1 then turns off while at
the same time comparator C2 turns on. With transistor N1
off, the capacitor C
EXT
begins to charge through the timing
resistor, R
EXT
, toward V
CC
. When the voltage across C
EXT
equals V
REF2
, comparator C2 changes state causing the
output latch to reset (Q goes LOW) while at the same time
disabling comparator C2. This ends the timing cycle with
the monostable in the quiescent state, waiting for the next
trigger.
A valid trigger is also recognized when trigger input B goes
from GND to V
CC
(while input A is at GND and input clear
is at V
CC
2). The MM74HC221 can also be triggered when
clear goes from GND to V
CC
(while A is at Gnd and B is at
V
CC
6).
It should be noted that in the quiescent state C
EXT
is fully
charged to V
CC
causing the current through resistor R
EXT
to be zero. Both comparators are “off” with the total device
current due only to reverse junction leakages. An added
feature of the MM74HC221 is that the output latch is set via
the input trigger without regard to the capacitor voltage.
Thus, propagation delay from trigger to Q is independent of
the value of C
EXT
, R
EXT
, or the duty cycle of the input
waveform.
The MM74HC221 is non-retriggerable and will ignore input
transitions on A and B until it has timed out 3 and 4.
RESET OPERATION
These one shots may be reset during the generation of the
output pulse. In the reset mode of operation, an input pulse
on clear sets the reset latch and causes the capacitor to be
fast charged to V
CC
by turning on transistor Q1 5. When
the voltage on the capacitor reaches V
REF2
, the reset latch
will clear and then be ready to accept another pulse. If the
clear input is held LOW, any trigger inputs that occur will be
inhibited and the Q and Q
outputs of the output latch will
not change. Since the Q output is reset when an input low
level is detected on the Clear input, the output pulse T can
be made significantly shorter than the minimum pulse width
specification.
