6
AT17C/LV002A
2280B–08/01
Pin Configurations
20
PLCC
Pin
32
TQFP
Pin Name I/O Description
2 31 DATA I/O Three-state data output for configuration. Open-collector bi-directional pin for programming.
4 2 DCLK I/O Clock output or clock input. Rising edges on DCLK increment the internal address counter
and present the next bit of data to the DATA pin. The counter is incremented only if the OE
input is held High, the nCS input is held Low, and all configuration data has not been
transferred to the target device (otherwise, as the master device, the DCLK pin drives Low).
5 4 WP1 I WRITE PROTECT (1). Used to protect portions of memory during programming. Disabled by
default due to internal pull-down resistor. This input pin is not used during FPGA loading
operations. See the “Programming Specification for Atmel’s Configuration EEPROMs”
application note for more details.
8 7 OE I Output enable (active High) and reset (active Low) when SER_EN
is High. A Low logic level
resets the address counter. A High logic level (with nCS Low) enables DATA and permits the
address counter to count. In the mode, if this pin is Low (reset), the internal oscillator
becomes inactive and DCLK drives Low. The logic polarity of this input is programmable and
must be programmed active High (RESET active Low) by the user during programming for
Altera applications.
9 10 nCS I Chip select input (active Low). A Low input (with OE High) allows DCLK to increment the
address counter and enables DATA to drive out. If the AT17A Series is reset with nCS Low,
the device initializes as the first (and master) device in a daisy chain. If the AT17A Series is
reset with nCS High, the device initializes as a subsequent AT17A Series device in the chain.
10 12 GND Ground pin. A 0.2 µF decoupling capacitor should be placed between the VCC and GND
pins.
12 15 nCASC O Cascade select output (active Low). This output goes Low when the address counter has
reached its maximum value. In a daisy chain of AT17A Series devices, the nCASC pin of one
device is usually connected to the nCS input pin of the next device in the chain, which
permits DCLK from the master configurator to clock data from a subsequent AT17A Series
device in the chain.
A2 I Device selection input, A2. This is used to enable (or select) the device during programming,
(i.e., when SER_EN
is Low; please refer to the “Programming Specification for Atmel’s
Configuration EEPROMs” application note for more details.)
15 20 READY O Open collector reset state indicator. Driven Low during power-up reset, released (tri-stated)
when power-up is complete. (Recommend a 4.7 kΩ pull-up on this pin if used.)
18 23 SER_EN
I Serial enable must be held High during FPGA loading operations. Bringing SER_EN Low
enables the 2-wire serial programming mode.
20 27 VCC +3.3V/+5V power supply pin
