CAT34TS00
www.onsemi.com
3
Table 4. A.C. CHARACTERISTICS (V
CC
= 1.7 V to 1.9 V, T
A
= −20°C to +125°C)
Symbol
Parameter
100 kHz 400 kHz
Units
Min Max Min Max
F
SCL
(Note 5) Clock Frequency 10 100 10 400 kHz
t
HIGH
High Period of SCL Clock 4 0.6
ms
t
LOW
Low Period of SCL Clock 4.7 1.3
ms
t
TIMEOUT
(Note 6) SMBus SCL Clock Low Timeout 25 35 25 35 ms
t
R
(Note 7) SDA and SCL Rise Time 1000 300 ns
t
F
(Note 7) SDA and SCL Fall Time 300 300 ns
t
SU:DAT
Input Data Setup Time 250 100 ns
t
SU:STA
START Condition Setup Time 4.7 0.6
ms
t
HD:STA
START Condition Hold Time 4 0.6
ms
t
SU:STO
STOP Condition Setup Time 4 0.6
ms
t
BUF
Bus Free Time Between STOP and START 4.7 1.3
ms
t
HD:DAT
Input Data Hold Time 0 0 ns
t
DH
(Note 7) Output Data Hold Time 120 3450 120 900 ns
T
i
(Note 7) Noise Pulse Filtered at SCL and SDA Inputs 50 50 ns
t
PU
(Note 8) Power-Up Delay to Valid Temperature Recording 100 100 ms
5. Timing reference points are set at 30%, respectively 70% of V
CC
, as illustrated in Figure 5. Bus loading must be such as to allow meeting
the V
IL
and V
OL
as well as all other timing requirements. The minimum clock frequency of 10 kHz is an SMBus recommendation; the minimum
operating clock frequency is limited only by the SMBus time−out. The device also meets the Fast and Standard I
2
C specifications, except
that T
i
and t
DH
are shorter.
6. For the CAT34TS00, the interface will reset itself and will release the SDA line if the SCL line stays low beyond the t
TIMEOUT
limit. The time−out
count takes place when SCL is low in the time interval between START and STOP.
7. In a “Wired−OR” system (such as I
2
C or SMBus), SDA rise time is determined by bus loading. Since each bus pull−down device must be
able to sink the (external) bus pull−up current (in order to meet the V
IL
and/or V
OL
limits), it follows that SDA fall time is inherently faster than
SDA rise time. SDA rise time can exceed the standard recommended t
R
limit, as long as it does not exceed t
LOW
− t
DH
− t
SU:DAT
, where t
LOW
and t
DH
are actual values (rather than spec limits). A shorter t
DH
leaves more room for a longer SDA t
R
, allowing for a more capacitive bus
or a larger bus pull−up resistor.
8. The first valid temperature recording can be expected after t
PU
at nominal supply voltage.
Table 5. PIN CAPACITANCE (T
A
= 25°C, V
CC
= 1.9 V, f = 400 kHz)
Symbol Parameter Test Conditions/Comments Min Max Unit
C
IN
SDA, EVENT Pin Capacitance V
IN
= 0 8 pF
Input Capacitance (other pins) V
IN
= 0 6 pF
Table 6. INPUT IMPEDANCE
Symbol Parameter Test Conditions Min Max Unit
Z
EIL
Input Impedance for A0, A1, A2 Pins V
IN
< 0.3 * V
CC
30
kW
Z
EIH
Input Impedance for A0, A1, A2 Pins V
IN
> 0.7 * V
CC
800
kW
