© Semiconductor Components Industries, LLC, 2016
April, 2017 − Rev. 0
1 Publication Order Number:
NLHV4051/D
NLHV4051, NLHV4052,
NLHV4053
Analog
Multiplexers/Demultiplexers
The NLHV4051, NLHV4052, and NLHV4053 analog multiplexers
are digitally−controlled analog switches. The NLHV4051 effectively
implements an SP8T solid state switch, the NLHV4052 a DP4T, and
the NLHV4053 a Triple SPDT. All three devices feature low ON
impedance and very low OFF leakage current. Control of analog
signals up to the complete supply voltage range can be achieved.
Features
• Triple Diode Protection on Control Inputs
• Switch Function is Break Before Make
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Analog Voltage Range (V
DD
− V
EE
) = 3.0 to 18 V
Note: V
EE
must be ≤ V
SS
• Linearized Transfer Characteristics
• Low−noise − 12 nV/√Cycle, f ≥ 1.0 kHz Typical
• Pin−for−Pin Replacement for CD4051, CD4052, and CD4053
• For 4PDT Switch, See MC14551B
• For Lower R
ON
, Use the HC4051, HC4052, or HC4053 High−Speed
CMOS Devices
• These Devices are Pb−Free and are RoHS Compliant
MAXIMUM RATINGS (Voltages Referenced to V
SS
)
Symbol
Parameter Value Unit
V
DD
DC Supply Voltage Range
(Referenced to V
EE
, V
SS
≥ V
EE
)
−0.5 to +18.0 V
V
in
,
V
out
Input or Output Voltage Range
(DC or Transient) (Referenced to V
SS
for
Control Inputs and V
EE
for Switch I/O)
−0.5 to V
DD
+ 0.5 V
I
in
Input Current (DC or Transient)
per Control Pin
+10 mA
I
SW
Switch Through Current ±25 mA
P
D
Power Dissipation per Package (Note 1) 500 mW
T
A
Ambient Temperature Range −55 to +125 °C
T
stg
Storage Temperature Range −65 to +150 °C
T
L
Lead Temperature (8−Second Soldering) 260 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Temperature Derating: “D/DW” Packages: –7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V
in
and V
out
should be constrained to
the range V
SS
≤ (V
in
or V
out
) ≤ V
DD
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either
V
SS
, V
EE
or V
DD
). Unused outputs must be left open.
www.onsemi.com
MARKING DIAGRAMS
SOIC−16
TSSOP−16
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
ORDERING INFORMATION
NLHVG
405x
AWLYWW
NLHV
405x
ALYWG
G
1
1
16
1
1
16
x = 1, 2, or 3
A = Assembly Location
WL, L = Wafer Lot
Y = Year
WW, W = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)
SOIC−16
D SUFFIX
CASE 751B
TSSOP−16
DT SUFFIX
CASE 948F