74LVC00A-Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 27 February 2013 6 of 14
NXP Semiconductors
74LVC00A-Q100
Quad 2-input NAND gate
10. Dynamic characteristics
[1] Typical values are measured at T
amb
=25C and V
CC
= 1.2 V, 1.8 V, 2.5 V, 2.7 V, and 3.3 V respectively.
[2] t
pd
is the same as t
PLH
and t
PHL
.
[3] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
[4] C
PD
is used to determine the dynamic power dissipation (P
D
in W).
P
D
=C
PD
V
CC
2
f
i
N+(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz; f
o
= output frequency in MHz
C
L
= output load capacitance in pF
V
CC
= supply voltage in Volts
N = number of inputs switching
(C
L
V
CC
2
f
o
) = sum of the outputs
11. Waveforms
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 7.
Symbol Parameter Conditions 40 C to +85 C 40 C to +125 C Unit
Min Typ
[1]
Max Min Max
t
pd
propagation delay nA, nB to nY; see Figure 6
[2]
V
CC
=1.2V - 12 - - - ns
V
CC
= 1.65 V to 1.95 V 0.3 3.8 8.4 0.3 9.7 ns
V
CC
= 2.3 V to 2.7 V 1.0 2.2 4.8 1.0 5.7 ns
V
CC
= 2.7 V 1.0 2.3 5.1 1.0 5.9 ns
V
CC
= 3.0 V to 3.6 V 0.5 2.0 4.3 0.5 5.1 ns
t
sk(o)
output skew time V
CC
= 3.0 V to 3.6 V
[3]
- - 1.0 - 1.5 ns
C
PD
power dissipation
capacitance
per gate; V
I
=GNDtoV
CC
[4]
V
CC
= 1.65 V to 1.95 V - 5.6 - - - pF
V
CC
= 2.3 V to 2.7 V - 8.9 - - - pF
V
CC
= 3.0 V to 3.6 V - 11.8 - - - pF
V
M
= 1.5 V at V
CC
2.7 V.
V
M
=0.5 V
CC
at V
CC
<2.7V.
V
OL
and V
OH
are typical output voltage levels that occur with the output load.
Fig 6. The input (nA, nB) to output (nY) propagation delays
mna213
nA, nB input
nY output
t
PHL
t
PLH
V
M
V
M
V
OL
V
OH
GND
V
I
