TEA6425
4/10
I
2
C BUS CHARACTERISTICS
Figure 4. I
2
C Bus Timing
Symbol Parameter Test Conditions
Standard Mode Fast Mode
Unit
Min. Max. Min. Max.
SCL
V
IL
Low Level Input Voltage - 0.3 + 1.5 - 0.3 + 1.5 V
V
IH
High Level Input Voltage 3.0 V
CC
+ 0.5 3.0 V
CC
+ 0.5 V
I
LI
Input Leakage Current V
I
= 0 to V
DD
- 10 + 10 - 10 + 10 µA
f
SCL
Clock Frequency 0 100 0 400 kHz
t
R
Input Rise Time 1.5V to 3V 1000 300 ns
t
F
Input Fall Time 1.5V to 3V 300 300 ns
C
I
Input Capacitance 10 10 pF
SDA
V
IL
Low Level Input Voltage - 0.3 + 1.5 - 0.3 + 1.5 V
V
IH
High Level Input Voltage 3.0 V
CC
+ 0.5 3.0 V
CC
+ 0.5 V
I
LI
Input Leakage Current V
I
= 0 to V
DD
- 10 + 10 - 10 + 10 µA
C
I
Input Capacitance 10 10 pF
t
R
Input Rise Time 1.5V to 3V 1000 300 ns
t
F
Input Fall Time 1.5V to 3V 300 300 ns
V
OL
Low Level Output Voltage I
OL
= 3mA 0.4 0.4 V
t
F
Output Fall Time 3V to 1.5V 250 250 ns
C
L
Load Capacitance 400 400 pF
TIMING
t
LOW
Clock Low Period 4.7 1.3 µs
t
HIGH
Clock High Period 4.0 0.6 µs
t
SU
, DAT Data Set-up Time 250 100 ns
t
HD
, DAT Data Hold Time 0 340 0 340 ns
t
SU
, STO Set-up Time from Clock High to Stop 4.0 0.6 µs
t
BUF
Start Set-up Time following a Stop 4.7 1.3 µs
t
HD
, STA Start Hold Time 4.0 0.6 µs
t
SU
, STA
Start Set-up Time following Clock Low-to
High Transition
4.7 0.6 µs
6425-04.eps
t
BUF
t
LOW
t
HIGH
t
f
t
r
t
HD,STA
t
HD,DAT
t
SU,DAT
t
SU,STA t
SU,STO
SDA
SCL
SDA
1
