NTHD4102P
http://onsemi.com
5
PACKAGE DIMENSIONS
ChipFET]
CASE 1206A−03
ISSUE K
Basic
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
STYLE 2:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
E
A
b
e
e1
D
1234
8765
c
L
1234
8765
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. MOLD GATE BURRS SHALL NOT EXCEED 0.13 MM PER SIDE.
4. LEADFRAME TO MOLDED BODY OFFSET IN HORIZONTAL
AND VERTICAL SHALL NOT EXCEED 0.08 MM.
5. DIMENSIONS A AND B EXCLUSIVE OF MOLD GATE BURRS.
6. NO MOLD FLASH ALLOWED ON THE TOP AND BOTTOM LEAD
SURFACE.
0.05 (0.002)
DIM
A
MIN NOM MAX MIN
MILLIMETERS
1.00 1.05 1.10 0.039
INCHES
b 0.25 0.30 0.35 0.010
c 0.10 0.15 0.20 0.004
D 2.95 3.05 3.10 0.116
E 1.55 1.65 1.70 0.061
e 0.65 BSC
e1 0.55 BSC
L 0.28 0.35 0.42 0.011
0.041 0.043
0.012 0.014
0.006 0.008
0.120 0.122
0.065 0.067
0.025 BSC
0.022 BSC
0.014 0.017
NOM MAX
1.80 1.90 2.00 0.071 0.075 0.079
H
E
5° NOM
q
5° NOM
H
E
q
RESET
0.457
0.018
2.032
0.08
0.65
0.025
PITCH
0.66
0.026
ǒ
mm
inches
Ǔ
2.362
0.093
1
8X
8X
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NTHD4102P/D
ChipFET is a trademark of Vishay Siliconix.
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