4
Figure 3. Recommended Decoupling and Termination Circuits
o
V
EE
R
X
o
V
CC
R
X
o
SD
o
RD-
o
RD+
Z = 50
Z = 50
TERMINATE AT
TRANSCEIVER INPUTS
Z = 50
Z = 50
10 9 8 7 6
SD
LVPECL
V
CC
(+3.3 V)
TERMINATE AT
DEVICE INPUTS
LVPECL
V
CC
(+3.3 V)
PHY DEVICE
TD+
TD-
RD+
RD-
V
CC
(+3.3 V)
Z = 50
1 2 3 4 5
TD-
o
TD+
o
N/C
o
V
EE
T
X
o
V
CC
T
X
o
1 µH
C2
1 µH
C1
C3
10 µF
V
CC
(+3.3 V)
T
X
R
X
Notes:
C1 = C2 = C3 = 10 nF or 100 nF
* Loading of R1 is optional.
100
100
130
130
130
130
LVTTL
130
82
Recommended Handing Precautions
Avago recommends that normal status precautions be
taken in the handling and assembly of these transceiv-
ers to prevent damage which may be induced by elec-
trostatic discharge (ESD). The HFBR-5961xxZ series of
transceivers meet MIL-STD-883C Method 3015.4 Class 2
products.
Care should be used to avoid shorting the receiver data
or signal detect outputs directly to ground without
proper current limiting impedance.
Solder and Wash Process Compatibility
The transceivers are delivered with protective process
plugs inserted into the LC receptacle.
This process plug protects the optical subassemblies
during wave solder and aqueous wash processing and
acts as a dust cover during shipping.
These transceivers are compatible with either industry
standard wave or hand solder processes.
Shipping Container
The transceiver is packaged in a shipping container
designed to protect it from mechanical and ESD
damage during shipment of storage.
Board Layout - Decoupling Circuit, Ground Planes and Termi-
nation Circuits
It is important to take care in the layout of your circuit
board to achieve optimum performance from these
transceivers. Figure 3 provides a good example of a
schematic for a power supply decoupling circuit that
works will with these parts, It is further recommend-
ed that a contiguous ground plane be provided in the
circuit board directly under the transceiver to provide
a low inductance ground for signal return current.
This recommendation is in keeping with good high
frequency board layout practices. Figures 3 and 4 show
two recommended termination schemes.
5
Board Layout - Hole Pattern
The Avago transceiver complies with the circuit board
“Common Transceiver Footprint” hole pattern dened in
the original multisource announcement which dened
the 2 x 5 package style. This drawing is reproduced in
Figure 6 with the addition of ANSI Y14.5M compliant
dimensioning to be used as a guide in the mechani-
cal layout of your circuit board. Figure 6 illustrates the
recommended panel opening and the position of the
circuit board with respect to this panel.
Figure 4. Alternative Termination Circuits
o
V
EE
R
X
o
V
CC
R
X
o
SD
o
RD-
o
RD+
Z = 50
130
V
CC
(+3.3 V)
10 nF
Z = 50
130
82 82
TERMINATE AT
TRANSCEIVER INPUTS
Z = 50
Z = 50
10 9 8 7 6
SD
LVPECL
V
CC
(+3.3 V)
TERMINATE AT DEVICE INPUTS
LVPECL
V
CC
(+3.3 V)
PHY DEVICE
TD+
TD-
RD+
RD-
Z = 50
1 2 3 4 5
TD-
o
TD
+
o
N/C
o
V
EE
T
X
o
V
CC
T
X
o
1 µH
C2
1 µH
C1
C3
10 µF
V
CC
(+3.3 V)
T
X
R
X
Note:
C1 = C2 = C3 = 10 nF or 100 nF
* Loading R1 is optional.
10 nF
130
82
V
CC
(+3.3 V)
130
82
V
CC
(+3.3 V)
10 nF
LVTTL
82
130
Regulatory Compliance
These transceiver products are intended to enable
commercial system designers to develop equipment
that complies with the various international regula-
tions governing certication of Information Technology
Equipment. See the Regulatory Compliance Table for
details. Additional information is available from your
Avago sales representative.
6
ALL DIMENSIONS IN MILIMETERS(INCHES)
Figure 5. Package Outline Drawing

HFBR-5961GZ

Mfr. #:
Manufacturer:
Broadcom / Avago
Description:
Fiber Optic Transmitters, Receivers, Transceivers OC3/FE LC SFF
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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