LTC1411IG#TRPBF Datasheet LTC1411CG#PBF, LTC1411IG#PBF, LTC1411IG#TRPBF | P10-P12

LTC1411

1411f

the sampling capacitor, choose an amplifier that has a low

output impedance (<100Ω) at the closed-loop bandwidth

frequency. For example, if an amplifier is used in a gain of

1 and has a unity-gain bandwidth of 50MHz, then the

output impedance at 50MHz must be less than 100Ω. The

second requirement is that the closed-loop bandwidth

must be greater than 40MHz to ensure adequate small-

signal settling for full throughput rate. If slower op amps

are used, more settling time can be provided by increasing

the time between conversions.

The best choice for an op amp to drive the LTC1411 will

depend on the application. Generally applications fall into

two categories: AC applications where dynamic specifica-

tions are most critical and time domain applications where

DC accuracy and settling time are most critical. The

following list is a summary of the op amps that are suitable

for driving the LTC1411. More detailed information is

available in the Linear Technology Databooks and on the

LinearView

CD-ROM.

1227: 140MHz Video Current Feedback Amplifier.

10mA supply current. ±5V to ±15V supplies. Low noise.

Good for AC applications.

LT1395: 400MHz Current Feedback Amplifier. Single 5V

or ±5V supplies. Good for AC applications.

LT1800: 80MHz, 25V/µs Low Power Rail-to-Rail Input and

Output Precision Op Amp. Specified at 3V, 5V and ±5V

supplies. Excellent DC performance.

Peak Harmonic or Spurious Noise

The peak harmonic or spurious noise is the largest spec-

tral component excluding the input signal and DC. This

value is expressed in dB relative to the RMS value of a full-

scale input signal.

Full-Power and Full-Linear Bandwidth

The full-power bandwidth is that input frequency at which

the amplitude of the reconstructed fundamental is re-

duced by 3db for a full-scale input signal.

The full-linear bandwidth is the input frequency at which

the S/(N + D) has dropped to 74dB (12 effective bits). The

LTC1411 has been designed to optimize input bandwidth,

allowing the ADC to undersample input signals with fre-

quencies above the converter’s Nyquist frequency. The

noise floor stays very low at high frequencies; S/(N + D)

becomes dominated by distortion at frequencies far be-

yond Nyquist.

Driving the Analog Input

The differential analog inputs of the LTC1411 are easy to

drive. The inputs may be driven differentially or as a single-

ended input (i.e., the A

–

input is tied to a fixed DC voltage

such as the REFOUT pin of the LTC1411 or an external

source). Figure 1 shows a simplified block diagram for the

analog inputs of the LTC1411. The A

and A

–

are

sampled at the same instant. Any unwanted signal that is

common mode to both inputs will be reduced by the

common mode rejection of the sample-and-hold circuit.

The inputs draw only one small current spike while charg-

ing the sample-and-hold capacitors at the end of conver-

sion. During conversion, the analog inputs draw only a

small leakage current. If the source impedance of the

driving circuits is low, then the LTC1411 inputs can be

driven directly. More acquisition time should be allowed

for a higher impedance source. Figure 5 shows the acqui-

sition time versus source resistance.

Choosing an Input Amplifier

Choosing an input amplifier is easy if a few requirements

are taken into consideration. First, to limit the magnitude

of the voltage spike seen by the amplifier from charging

APPLICATIO S I FOR ATIO

WUUU

SOURCE RESISTANCE (Ω)

ACQUISITION TIME (µs)

10000

1411 G16

0.1

0.01

100

1000

100000

100

Figure 5. Acquisition Time vs Source Resistance

LinearView is a trademark of Linear Technology Corporation.

LTC1411

1411f

LT6203: Dual 100MHz, Low Noise, Low Power Op Amp.

Specified at 3V, 5V and ±5V supplies. 1.9nV/√Hz noise

voltage.

Programmable Input Range

The LTC1411 has two logic input pins (PGA0 and PGA1)

that are used to select one of four analog input ranges.

These input ranges are set by changing the reference

voltage that is applied to the internal DAC of the ADC

(REFCOM2). For the “0dB” setting the internal DAC sees

the full reference voltage of 4V. The analog input range is

0.7V to 4.3V with A

–

= 2.5V. This corresponds to an input

span of ±1.8V with respect to the voltage applied to A

–

. For the “–3dB” setting the internal reference is reduced

to 0.707 • 4V = 2.9V. Likewise the input span is reduced

to ±1.28V. The following table lists the input span with

respect to A

–

for the different PGA0 and PGA1 settings.

Table 1. Input Spans for LTC1411

INPUT REFCOM2

PGA0 PGA1 LEVEL SPAN VOLTAGE

5V 5V 0dB ±1.8V 4V

5V 0V –3dB ±1.28V 2.9V

0V 5V – 6dB ±0.9V 2V

0V 0V –9dB ±0.64V 1.45V

When changing from one input span to another, more time

is needed for the REFCOM2 pin to reach the correct level

because the bypass capacitor on the pin needs to be charged

or discharged. Figure 6 shows the recommended capaci-

tors at the REFCOM1 and REFCOM2 pins (10µF each).

When –6dB or –9dB is selected, the voltage at REFCOM1

(see Figure 2) must first settle before REFCOM2 reaches

the correct level. The typical delay is about 700ms.

When the REFCOM2 level is changed from 2.9V to 4V

(changing PGA setting from – 3dB to 0dB), the typical delay

is 0.6ms. However, if the voltage at REFCOM2 is changed

from 4V to 2.9V (changing PGA setting from 0dB to –3dB)

only a 60µA sink current is present to discharge the 10µF

bypass capacitor. In this case, the delay will be 11ms.

Internal Reference

The LTC1411 has an on-chip, temperature compensated,

curvature corrected, bandgap reference that is factory

trimmed to 2.500V. If this REFOUT pin is used to drive the

–

pin, a 22µF tantalum bypass capacitor is required and

this REFOUT voltage sets the bipolar zero for the ADC.

The REFIN pin is connected to the reference buffer through

a 2k resistor and two PGA switches. The REFIN pin can be

connected to REFOUT directly or to an external reference.

Figure 6 shows the reference and buffer structure for the

LTC1411. The input to the reference buffer is either REFIN

or 1/2 of REFIN depending on the PGA selection. The

REFCOM1 pin bypassed with a 10µF tantalum capacitor

helps reduce the noise going into the buffer. The reference

buffer has a gain of 1.62 or 1.15 (depends on PGA

selection). It is compensated at the REFCOM2 pin with a

10µF tantalum capacitor. The input span of the ADC is set

by the output voltage of this REFCOM2 voltage. For a 2.5V

input at the REFIN pin, the REFCOM2 will have 4V output

for PGA1 = PGA0 = 5V and the ADC will have a span of 3.6V.

APPLICATIO S I FOR ATIO

WUUU

Figure 6. Reference Structure for the LTC1411

for PGA1 = PGA0 = 5V

REFCOM2

10µF

1411 F06

REFCOM1

REFIN*

REFOUT

10µF

THIS PIN CAN BE TIED TO REFOUT OR AN EXTERNAL SOURCE

A 22µF CAPACITOR IS NEEDED IF REFOUT IS USED TO DRIVE A

–

22µF**

2.5V

BANDGAP

REFERENCE

X1.62

LTC1411

1411f

Figure 7 shows a typical reference, the LT1019A-2.5

connected to the LTC1411. This will provide an improved

drift (equal to the maximum 5ppm/°C of the LT1019A-2.5).

By driving the SLP pin low for Sleep mode, the ADC shuts

down to less than 1µA. After release from the Sleep mode,

the ADC needs 210ms (10µF bypass capacitor on the

REFCOM2 pin) to wake up.

In Nap mode, all the power is off except the internal refer-

ence which is still active for the other external circuitry. In

this mode the ADC draws about 2mA instead of 39mA (for

minimum power, the logic inputs must be within 600mV

from the supply rails). The wake-up time from Nap mode

to active state is 250ns as shown in Figure 9.

Board Layout and Bypassing

Wire wrap boards are not recommended for high resolu-

tion or high speed A/D converters. To obtain the best

performance from the LTC1411, a printed circuit board

with a ground plane is required. Layout for the printed

circuit board should ensure that the digital and analog

signal lines are separated as much as possible. In particu-

lar, care should be taken not to run any digital track

alongside an analog signal track.

APPLICATIO S I FOR ATIO

WUUU

Figure 9. NAP to CONVST Wake-Up Timing

Figure 7. Supplying a 2.5V Reference Voltage

to the LTC1411 with the LT1019A-2.5

Figure 8. Overrange and Underrange Logic

Table 2. Out-of-the-Range Truth Table

OTR D13 (MSB) ANALOG INPUT

0 0 In Range

0 1 In Range

1 0 Overrange

1 1 Underrange

3Ω

7, 8, 9

INPUT RANGE:

0.7V TO 4.3V

10µF

1411 F07

LT1019A-2.5

GND

OUT

LTC1411

–

AGND

REFIN

Digital Interface

The ADC has a very simple digital interface with only one

control input, CONVST. A logic low applied to the CONVST

input will initiate a conversion. The ADC presents digital

data in 2’s complement format with bipolar zero set by the

voltage applied to the A

–

pin.

Internal Clock

The internal clock is factory trimmed to achieve a typical

conversion time of 260ns. With the typical acquisition

time of 100ns, a throughput sampling rate of 2.5Msps is

guaranteed.

Out-of-the-Range Signal (OTR)

The LTC1411 has a digital output, OTR, that indicates if an

analog input signal is out of range. The OTR remains

low when the analog input is within the specified range.

Once the analog signal goes to the most negative input

(1000 0000 0000 00) or 64LSB above the specified most

positive input, OTR will go high. By NORing D13 (MSB)

and its complement with OTR, overrange and underrange

can be detected as shown in Figure 8. Table 2 is the truth

table of the out-of-the-range circuit in Figure 8.

Power Shutdown (Sleep and Nap Modes)

The LTC1411 provides two shutdown features that will

save power when the ADC is inactive.

OTR

D13

“1” FOR OVERRANGE

U1-A

U1-B

U1-A, U1-B = 74HC OR EQUIVALENT

“1” FOR UNDERRANGE

1411 F08

NAP

CONVST

1411 F09

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P16

LTC1411IG#TRPBF

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Description:

Analog to Digital Converters - ADC 1x S 14-B 2.5Msps ADC

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LTC1411IG#TRPBF

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