MAX1954A
Low-Cost, Current-Mode PWM Buck
Controller with Foldback Current Limit
______________________________________________________________________________________ 13
choose the high-side MOSFET (N1) that has conduction
losses equal to switching loss at nominal input voltage
and output current. The selected MOSFETs must have an
R
DS(ON)
that satisfies the current-limit setting condition
above. For N2, ensure that it does not spuriously turn on
due to dV/dt caused by N1 turning on, as this would
result in shoot-through current degrading the efficiency.
MOSFETs with a lower Q
gd
/Q
gs
ratio have higher immuni-
ty to dV/dt.
For proper thermal-management design, the power dis-
sipation must be calculated at the desired maximum
operating junction temperature, T
J(MAX)
. N1 and N2
have different loss components due to the circuit oper-
ation. N2 operates as a zero-voltage switch; therefore,
major losses are the channel-conduction loss (P
N2CC
)
and the body-diode conduction loss (P
N2DC
).
where V
F
is the body-diode forward-voltage drop, t
dt
is
the dead time between N1 and N2 switching transitions,
f
S
is the switching frequency, and t
dt
is 20ns (typ).
N1 operates as a duty-cycle control switch and has the
following major losses: the channel-conduction loss
(P
N1CC
), the VL overlapping switching loss (P
N1SW
),
and the drive loss (P
N1DR
). N1 does not have body-
diode conduction loss, because the diode never con-
ducts current.
where I
GATE
is the average DH-driver output current
capability determined by:
where R
DS(ON)(N2)
is the high-side MOSFET driver’s
on-resistance (1.5 typ) and R
GATE
is the internal gate
resistance of the MOSFET (~2).
where V
GS
~V
IN.
In addition to the losses above, allow approximately
20% for additional losses due to MOSFET output capac-
itances and N2 body-diode reverse-recovery charge
dissipated in N1 that exists, but is not well defined, in
the MOSFET data sheet. Refer to the MOSFET data
sheet for thermal-resistance specification to calculate
the PC board area needed to maintain the desired maxi-
mum operating junction temperature with the above cal-
culated power dissipations.
To reduce electromagnetic interference (EMI) caused
by switching noise, add a 0.1µF ceramic capacitor from
the high-side switch drain to the low-side switch source
or add resistors in series with DH and DL to slow down
the switching transitions. However, adding series resis-
tors increases the power dissipation of the MOSFET, so
be sure this does not overheat the MOSFET.
The minimum load current must exceed the high-side
MOSFET’s maximum leakage-current overtemperature
if fault conditions are expected.
MOSFET Snubber Circuit
Fast-switching transitions cause ringing because of
resonating circuit parasitic inductance and capaci-
tance at the switching nodes. This high-frequency ring-
ing occurs at LX’s rising and falling transitions and can
interfere with circuit performance and generate EMI. To
dampen this ringing, a series RC snubber circuit is
added across each switch. Below is the procedure for
selecting the value of the series RC circuit:
1) Connect a scope probe to measure the voltage
from LX to GND, and observe the ringing frequen-
cy, f
R
.
2) Find the capacitor value (connected from LX to
GND) that reduces the ringing frequency by half.
The circuit parasitic capacitance (C
PAR
) at LX is then
equal to 1/3rd of the value of the added capacitance
above. The circuit parasitic inductance (L
PAR
) is calculat-
ed by:
The resistor for critical dampening (R
SNUB
) is equal to
2π x f
R
x L
PAR
. Adjust the resistor value up or down to
tailor the desired damping and the peak voltage excur-
sion. The capacitor (C
SNUB
) should be at least two to
four times the value of the C
PAR
to be effective. The
power loss of the snubber circuit (P
RSNUB
) is dissipat-
ed in the resistor R
SNUB
and can be calculated as:
PCVf
RSNUB SNUB IN S
()
×
2
L
fC
PAR
R PAR
=
()
×
1
2
2
π
PQVf
R
RR
NDR g GS
S
GATE
GATE DS ON N
1
2
××
+
()()
I
V
RR
GATE
IN
DS ON N GATE
.
()()
≅×
+
05
2
.
()
() ( )
P
V
V
IR
Use R at T
PVI
QQ
I
f
NCC
OUT
IN
LOAD
DS ON
DS ON J MAX
N SW IN LOAD
gs gd
GATE
S
1
2
1
=
××
×
+
×
(
.
() ( )
() ( )
VR I
LIR
I
Use R at T
PIVtf
VALLEY DS ON LOAD MAX LOAD MAX
DS ON J MAX
N DC LOAD F dt S
×
× × ×
()
2
2
2
MAX1954A
Low-Cost, Current-Mode PWM Buck
Controller with Foldback Current Limit
14 ______________________________________________________________________________________
where V
IN
is the input voltage and f
S
is the switching
frequency. Choose a R
SNUB
power rating that meets
the specific application’s derating rule for the power
dissipation calculated.
Input Capacitor
The input filter capacitor reduces peak currents drawn
from the power source and reduces noise and voltage
ripple on the input caused by the circuit’s switching.
The input capacitor must meet the ripple current
requirement (I
RMS
) imposed by the switching currents
defined by the following equation:
I
RMS
has a maximum value when the input voltage
equals twice the output voltage (V
IN
= 2 x V
OUT
); there-
fore, I
RMS(MAX)
= I
LOAD
/ 2. Ceramic capacitors are
recommended due to their low equivalent series resis-
tance (ESR) and equivalent series inductance (ESL) at
high frequencies, and their relatively low cost. Choose
a capacitor that exhibits less than 10°C temperature
rise at the maximum operating root-mean-square (RMS)
current for optimum long-term reliability.
Output Capacitor
The key selection parameters for the output capacitor
are the actual capacitance value, ESR, ESL, and the
voltage-rating requirements. These parameters affect
the overall stability, output voltage ripple, and transient
response. The output ripple has three components: vari-
ations in the charge stored in the output capacitor, and
the voltage drop across the capacitor’s ESR and ESL
caused by the current into and out of the capacitor. The
equation below estimates the maximum ripple voltage:
The output voltage ripple as a consequence of the ESR,
output capacitance, and ESL are as follows:
where I
P-P
is the peak-to-peak inductor current (see the
Inductor Value section). These equations are suitable
for initial capacitor selection, but final values should be
chosen based on a prototype or evaluation circuit. As a
general rule, a smaller current ripple results in less out-
put voltage ripple. Since the inductor ripple current is a
factor of the inductor value and input voltage, the out-
put voltage ripple decreases with larger inductance,
and increases with higher input voltages. For the
MAX1954A polymer, tantalum, or aluminum electrolytic
capacitors are recommended. Lower-cost aluminum
electrolytic capacitors with relatively low ESR are avail-
able and can be used for the MAX1954A, if the larger
physical size is acceptable. For reliable and safe oper-
ation, ensure that the capacitor’s voltage and ripple-
current ratings exceed the calculated values.
The devices’ response to a load transient depends on
the selected output capacitors. After a load transient,
the output voltage instantly changes by ESR x I
LOAD
.
Before the controller can respond, the output voltage
deviates further depending on the inductor and output
capacitor values. After a short period of time (see the
Typical Operating Characteristics), the controller
responds by regulating the output voltage back to its
nominal state. The controller response time depends on
its closed-loop bandwidth. With a higher bandwidth, the
response time is faster, thus preventing the output volt-
age from deviating further from its regulation value.
Compensation Design
The MAX1954A uses an internal transconductance
error amplifier whose output compensates the control
loop. The external inductor, high-side MOSFET, output
capacitor, compensation resistor, and compensation
capacitors determine the loop stability. The inductor
and output capacitors are chosen based on perfor-
mance, size, and cost. Additionally, the compensation
resistor and capacitors are selected to optimize control-
loop stability. The component values in Figures 1 and 2
yield stable operation over the given range of input-to-
output voltages and load currents. The controller uses a
current-mode control scheme that regulates the output
voltage by forcing the required current through the
external inductor. The MAX1954A uses the voltage
across the high-side MOSFET’s on-resistance
(R
DS(ON)
) to sense the inductor current. Current-mode
control eliminates the double pole in the feedback loop
caused by the inductor and output capacitor, resulting
in a smaller phase shift and requiring less elaborate
error-amplifier compensation. A single-series compen-
sation resistor (R
C
) and compensation capacitor (C
C
) is
all that is needed to have a stable high-bandwidth loop
in applications where ceramic capacitors are used for
V I ESR
V
I
Cf
V
V
L
ESL
I
VV
fL
V
V
RIPPLE
ESR
PP
RIPPLE C
PP
OUT
S
RIPPLE ESL
IN
PP
IN OUT
S
OUT
IN
()
()
()
=
××
×
=
×
×
=
8
VV V V
RIPPLE RIPPLE
ESR
RIPPLE C RIPPLE ESL
=++
()
() ( )
I
IVVV
V
RMS
LOAD OUT IN OUT
IN
=
××
()
MAX1954A
Low-Cost, Current-Mode PWM Buck
Controller with Foldback Current Limit
______________________________________________________________________________________ 15
output filtering. For other types of capacitors, due to the
higher capacitance and ESR, the frequency of the zero
created by the capacitance and ESR is lower than the
desired closed-loop crossover frequency. Another
compensation capacitor should be added to cancel
this zero.
The basic regulator loop can be thought of as a power
modulator, output feedback divider, and an error ampli-
fier. The power modulator has DC gain set by g
mc
x
R
LOAD
, with a pole and zero pair set by R
LOAD
, the out-
put capacitor (C
OUT
) and its equivalent series resis-
tance (R
ESR
). Below are equations that define the
power modulator:
where R
LOAD
= V
OUT
/ I
OUT(MAX)
, and g
mc
= 1 / (A
CS
x
R
DS(ON)
), where A
CS
is the gain of the current-sense
amplifier and R
DS(ON)
is the on-resistance of the high-
side power MOSFET. A
CS
is 3.5. The frequencies at
which the pole and zero due to the power modulator
occur are determined as follows:
The feedback voltage-divider used has a gain of G
FB
=
V
FB
/ V
OUT
, where V
FB
is equal to 0.8V. The transcon-
ductance error amplifier has DC gain, G
EA(DC)
= g
m
x
R
O
. The amplifier output resistance (R
O
) is typically
10M. The C
C
, R
O
, and the R
C
set a dominant pole.
The R
C
and the C
C
set a zero. There is an optional pole
set by C
F
and R
C
to cancel the output-capacitor ESR
zero if it occurs before crossover frequency (f
C
):
The f
C
should be much higher than the power modula-
tor pole f
PMOD
. Also, the crossover frequency should
be less than 1/8th of the switching frequency:
Therefore, the loop-gain equation at the crossover fre-
quency is:
When f
zMOD
is greater than f
C
:
then R
C
is calculated as:
where g
mEA
= 110µs.
The error-amplifier compensation zero formed by R
C
and C
C
should be set at the modulator pole f
pMOD
. C
C
is calculated by:
If f
zMOD
is less than 5 x f
C
, add a second compensa-
tion capacitor, C
f
, from COMP to GND to cancel the
ESR zero. C
f
is calculated by:
As the load current decreases, the modulator pole also
decreases. However, the modulator gain increases
accordingly and the crossover frequency remains
the same.
When f
zMOD
is less than f
C
, the power-modulator gain
at f
C
is:
GG
f
f
MOD fC MOD DC
pMOD
zMOD
() ( )
C
Rf
f
C zMOD
=
××
1
2π
C
RfLC
RfLR
C
LOAD
S
OUT
LOAD
S
C
=
×××
()
×
( )
R
V
gVG
C
OUT
mEA FB MOD fC
=
××
()
G g R and G g R
f
f
EA fC mEA C MOD fC mc LOAD
pMOD
C
() ()
=××
GG
V
V
EA fC MOD fC
FB
OUT
() ()
××=1
ff
f
pMOD C
S
<< <
8
f
CRR
f
CR
f
CR
pdEA
COC
zEA
CC
pEA
FC
=
××+
=
××
=
××
1
2
1
2
1
2
π
π
π
()
f
C
RfL
RfL
R
f
CR
pMOD
OUT
LOAD
S
LOAD
S
ESR
zMOD
OUT ESR
=
××
××
+
=
××
1
2
1
2
π
π
Gg
RfL
RfL
MOD mc
LOAD
S
LOAD
S
××

MAX1954AEUB+T

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Switching Controllers Current-Mode PWM Buck Controller
Lifecycle:
New from this manufacturer.
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