R1WV6416R Series
REJ03C0368-0100, Rev.1.00, 2009.05.07
Page 9 of 16
Write Cycle
R1WV6416R**-5S R1WV6416R**-7S
Parameter Symbol
Min. Max. Min. Max.
Unit Note
Write cycle time t
WC
55 - 70 - ns
Address valid to end of write t
AW
50 - 65 - ns
Chip select to end of write t
CW
50 - 65 - ns 5
Write pulse width t
WP
40 - 55 - ns 4
LB#, UB# valid to end of write t
BW
50 - 65 - ns
Address setup time t
AS
0 - 0 - ns 6
Write recovery time t
WR
0 - 0 - ns 7
Data to write time overlap t
DW
25 - 35 - ns
Data hold from write time t
DH
0 - 0 - ns
Output enable from end of write t
OW
5 - 5 - ns 2
Output disable to output in high-Z t
OHZ
0 20 0 25 ns 1,2
Write to output in high-Z t
WHZ
0 20 0 25 ns 1,2
Note1. t
CHZ
, t
OHZ
, t
WHZ
and t
BHZ
are defined as the time at which the outputs achieve the open circuit
conditions and are not referred to output voltage levels.
2. This parameter is sampled and not 100% tested.
3. At any given temperature and voltage condition, t
HZ
max is less than t
LZ
min both for a given device and
from device to device.
4. A write occurs during the overlap of a low CS1#, a high CS2, a low WE# and a low LB# or a low UB#.
A write begins at the latest transition among CS1# going low, CS2 going high, WE# going low and LB# going
low or UB# going low .
A write ends at the earliest transition among CS1# going high, CS2 going low, WE# going high and LB#
going high or UB# going high. t
WP
is measured from the beginning of write to the end of write.
5. t
CW
is measured from the later of CS1# going low or CS2 going high to end of write.
6. t
AS
is measured the address valid to the beginning of write.
7. t
WR
is measured from the earliest of CS1# or WE# going high or CS2 going low to the end of write cycle.
