AS7C31024B-10TCN

March 2004
Copyright © 2003 Alliance Semiconductor. All rights reserved.
®
AS7C31024B
3.3V 128K X 8 CMOS SRAM
3/24/04, v.1.2 Alliance Semiconductor P. 1 of 9
Features
Industrial and commercial temperatures
Organization: 131,072 words x 8 bits
High speed
- 10/12/15/20 ns address access time
- 5, 6, 7, 8 ns output enable access time
Low power consumption: ACTIVE
- 252 mW / max @ 10 ns
Low power consumption: STANDBY
- 18 mW / max CMOS
6T 0.18u CMOS technology
Easy memory expansion with CE1
, CE2, OE inputs
TTL/LVTTL-compatible, three-state I/O
32-pin JEDEC standard packages
- 300 mil SOJ
- 400 mil SOJ
- 8 × 20mm TSOP 1
- 8 x 13.4mm sTSOP 1
ESD protection 2000 volts
Latch-up current 200 mA
Logic block diagram
512 x 256 x 8
Array
(1,048,576)
Sense amp
Input buffer
A10
A11
A12
A13
A14
A15
A16
I/O0
I/O7
OE
CE1
WE
Column decoder
Row decoder
Control
circuit
A9
A0
A1
A2
A3
A4
A5
A6
A7
V
CC
GND
A8
CE2
Pin arrangement
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
AS7C31024B
32-pin SOJ (300 mil)
V
CC
A15
CE2
WE
A13
A8
A9
A11 OE
A10
CE1
I/O7
I/O6
I/O4
NC
A16
A14
A12
A7
A6
A5
A4 A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
I/O5
I/O3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
32
31
30
29
28
27
26
25
24
23
22
21
AS7C31024B
20
19
15
16
18
17
32-pin (8 x 20mm) TSOP I
32-pin SOJ (400 mil)
32-pin (8 x 13.4mm) sTSOP1
Selection guide
-10
-12 -15 -20 Unit
Maximum address access time 10 12 15 20 ns
Maximum output enable access time 5 6 7 8 ns
Maximum operating current 70656055mA
Maximum CMOS standby current 5 5 5 5 mA
AS7C31024B
3/24/04, v.1.2 Alliance Semiconductor P. 2 of 9
®
Functional description
The AS7C31024B is a high performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) device organized as 131,072 words
x 8 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired.
Equal address access and cycle times (t
AA
, t
RC
, t
WC
) of 10/12/15/20 ns with output enable access times (t
OE
) of 5, 6, 7, 8 ns are ideal for
high performance applications. Active high and low chip enables (CE1, CE2) permit easy memory expansion with multiple-bank systems.
When CE1 is high or CE2 is low, the device enters standby mode. If inputs are still toggling, the device will consume I
SB
power. If the bus is
static, then full standby power is reached (I
SB1
). For example, the AS7C31024B is guaranteed not to exceed 18 mW under nominal full
standby conditions.
A write cycle is accomplished by asserting write enable (WE) and both chip enables (CE1, CE2). Data on the input pins I/O0 through I/O7 is
written on the rising edge of WE
(write cycle 1) or the active-to-inactive edge of CE1 or CE2 (write cycle 2). To avoid bus contention,
external devices should drive I/O pins only after outputs have been disabled with output enable (OE
) or write enable (WE).
A read cycle is accomplished by asserting output enable (OE
) and both chip enables (CE1, CE2), with write enable (WE) high. The chip
drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write enable is
active, output drivers stay in high-impedance mode.
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and func-
tional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect reliability.
Key: X = don’t care, L = low, H = high
Absolute maximum ratings
Parameter Symbol Min Max Unit
Voltage on V
CC
relative to GND V
t1
-0.50 +5.0 V
Voltage on any pin relative to GND V
t2
–0.50 V
CC
+0.50 V
Power dissipation P
D
–1.0W
Storage temperature (plastic) T
stg
–65 +150 °C
Ambient temperature with V
CC
applied T
bias
–55 +125 °C
DC current into outputs (low) I
OUT
–20mA
Truth table
CE1
CE2
WE OE
Data Mode
HXXX High Z Standby (I
SB
, I
SB1
)
X L X X High Z Standby (I
SB
, I
SB1
)
L H H H High Z Output disable (I
CC
)
LHHL D
OUT
Read (I
CC
)
LHLX D
IN
Write (
ICC
)
AS7C31024B
3/24/04, v.1.2 Alliance Semiconductor P. 3 of 9
®
Recommended operating conditions
Parameter Symbol Min Nominal Max Unit
Supply voltage V
CC
3.0 3.3 3.6 V
Input voltage V
IH
2.0 V
CC
+ 0.5 V
V
IL
–0.5 0.8 V
Ambient operating temperature commercial T
A
0–70°C
V
IL
= -1.0V for pulse width less than 5ns
V
IH =
V
CC
+ 1.5V for pulse width less than 5ns
DC operating characteristics (over the operating range)
1
Parameter Sym Test conditions
-10 -12 -15 -20
Unit
Min Max Min Max Min Max Min Max
Input leakage
current
|I
LI
|
V
CC
= Max, V
IN
= GND to V
CC
–1–1–1–1µA
Output leakage
current
|I
LO
|
V
CC
= Max, CE1 = V
IH
or
CE2 = V
IL
, V
OUT
= GND to V
CC
–1–1–1–1µA
Operating power
supply current
I
CC
V
CC
= Max, CE1 V
IL
,
CE2 V
IH
, f = f
Max
,
I
OUT
= 0 mA
–70–65–60–55
mA
Standby power
supply current
I
SB
V
CC
= Max, CE1 V
IH
and/or
CE2 V
IL
, f = f
Max
–30–25–20–20
mA
I
SB1
V
CC
= Max, CE1 V
CC
–0.2V and/
or CE2 ≤ 0.2V
V
IN
0.2V or
V
IN
V
CC
–0.2V, f = 0
–5–5–5–5
Output voltage
V
OL
I
OL
= 8 mA, V
CC
= Min
–0.4–0.4–0.4–0.4V
V
OH
I
OH
= –4 mA, V
CC
= Min
2.4–2.4–2.4–2.4– V
Capacitance (f = 1 MHz, T
a
= 25 °C, V
CC
= NOMINAL)
2
Parameter Symbol Signals Test conditions Max Unit
Input capacitance C
IN
A, CE1, CE2, WE, OE V
IN
= 0V 5 pF
I/O capacitance C
I/O
I/O V
IN
= V
OUT
= 0V 7 pF

AS7C31024B-10TCN

Mfr. #:
Manufacturer:
Alliance Memory
Description:
SRAM 1M, 3.3V, 10ns, FAST 128K x 8 Asynch SRAM
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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