OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

AS7C31024B-10TJCNTR

P1-P3P4-P6P7-P9
AS7C31024B
3/24/04, v.1.2 Alliance Semiconductor P. 4 of 9
®
Key to switching waveforms
Read waveform 1 (address controlled)
3,6,7,9,12
Read waveform 2 (CE1, CE2, and OE controlled)
3,6,8,9,12
Read cycle (over the operating range)
3,9,12
Parameter Symbol
-10 -12 -15 -20
Unit NotesMin Max Min Max Min Max Min Max
Read cycle time t
RC
10–12–15–20 ns
Address access time t
AA
– 10 – 12 – 15 – 20 ns 3
Chip enable (CE1
) access time t
ACE1
– 10 – 12 – 15 – 20 ns 3, 12
Chip enable (CE2) access time t
ACE2
– 10 – 12 – 15 – 20 ns 3, 12
Output enable (OE
) access time t
OE
–5–6–7–8ns
Output hold from address change t
OH
3–3–3–3– ns 5
CE1
low to output in low Z t
CLZ1
3–3–3–3– ns 4, 5, 12
CE2 high to output in low Z t
CLZ2
3–3–3–3– ns 4, 5, 12
CE1
high to output in high Z t
CHZ1
–3–3–4– 5 ns 4, 5, 12
CE2 low to output in high Z t
CHZ2
–3–3–4– 5 ns 4, 5, 12
OE
low to output in low Z t
OLZ
0–0–0–0–ns4, 5
OE
high to output in high Z t
OHZ
–5–6–7–8ns4, 5
Power up time t
PU
0–0–0–0–ns4, 5, 12
Power down time t
PD
– 10 – 12 – 15 – 20 ns 4, 5, 12
Undefined / don’t careFalling inputRising input
Address
D
OUT
Data valid
t
OH
t
AA
t
RC
Supply
current
CE2
OE
D
OUT
t
OE
t
OLZ
t
ACE1
,
tACE2
t
CHZ1
, t
CHZ2
t
CLZ1
, t
CLZ2
t
PU
t
PD
I
CC
I
SB
50% 50%
Data valid
t
RC1
CE1
t
OHZ
AS7C31024B
3/24/04, v.1.2 Alliance Semiconductor P. 5 of 9
®
Write waveform 1 (WE controlled)
10,11,12
Write cycle (over the operating range)
11, 12
Parameter Symbol
-10 -12 -15 -20
Unit NotesMin Max Min Max Min Max Min Max
Write cycle time t
WC
10–12–15–20–ns
Chip enable (CE1
) to write end t
CW1
8–9–10–12–ns12
Chip enable (CE2) to write end t
CW2
8–9–10–12–ns12
Address setup to write end t
AW
8–9–10–12–ns
Address setup time t
AS
0–0–0–0–ns12
Write pulse width t
WP
7–8–9–12–ns
Write recovery time t
WR
0–0–0–0–ns
Address hold from end of write t
AH
0–0–0–0–ns
Data valid to write end t
DW
5–6–8–10–ns
Data hold time t
DH
0–0–0–0–ns4, 5
Write enable to output in high Z t
WZ
–5–6–7–8ns4, 5
Output active from write end t
OW
1–1–1–1–ns4, 5
t
AW
t
AH
t
WC
Address
WE
D
OUT
t
DH
t
OW
t
DW
t
WZ
t
WP
t
AS
Data valid
D
IN
t
WR
AS7C31024B
3/24/04, v.1.2 Alliance Semiconductor P. 6 of 9
®
Write waveform 2 (CE1 and CE2 controlled)
10,11,12
AC test conditions
Notes
1 During V
CC
power-up, a pull-up resistor to V
CC
on CE1 is required to meet I
SB
specification.
2 This parameter is sampled and not 100% tested.
3 For test conditions, see AC Test Conditions, Figures A, and B.
4t
CLZ
and t
CHZ
are specified with CL = 5pF, as in Figure C. Transition is measured ±500 mV from steady-state voltage.
5 This parameter is guaranteed, but not 100% tested.
6WE
is high for read cycle.
7CE1
and OE are low and CE2 is high for read cycle.
8 Address valid prior to or coincident with CE1
transition Low.
9 All read cycle timings are referenced from the last valid address to the first transitioning address.
10 N/A
11 All write cycle timings are referenced from the last valid address to the first transitioning address.
12 CE1
and CE2 have identical timing.
13 C = 30 pF, except all high Z and low Z parameters where C = 5 pF.
14 N/A
t
AW
Address
CE1
WE
D
OUT
t
CW1
, t
CW2
t
WP
t
DW
t
DH
t
AH
t
WC
t
AS
CE2
Data valid
D
IN
t
WR
t
WZ
255
Ω
– Output load: see Figure B.
– Input pulse level: GND to 3.0V. See Figure A.
– Input rise and fall times: 2 ns. See Figure A.
– Input and output timing reference levels: 1.5V.
C
13
320
Ω
D
OUT
GND
+3.3V
168
Ω
Thevenin equivalent:
D
OUT
+1.728V
Figure B: 3.3V Output load
10%
90%
10%
90%
GND
+3.0V
Figure A: Input pulse
2 ns
P1-P3P4-P6P7-P9

AS7C31024B-10TJCNTR

Mfr. #:
Buy AS7C31024B-10TJCNTR
Manufacturer:
Alliance Memory
Description:
SRAM 1M, 3.3V, 10ns, FAST 128K x 8 Asynch SRAM
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet