AS7C31024B
3/24/04, v.1.2 Alliance Semiconductor P. 6 of 9
®
Write waveform 2 (CE1 and CE2 controlled)
10,11,12
AC test conditions
Notes
1 During V
CC
power-up, a pull-up resistor to V
CC
on CE1 is required to meet I
SB
specification.
2 This parameter is sampled and not 100% tested.
3 For test conditions, see AC Test Conditions, Figures A, and B.
4t
CLZ
and t
CHZ
are specified with CL = 5pF, as in Figure C. Transition is measured ±500 mV from steady-state voltage.
5 This parameter is guaranteed, but not 100% tested.
6WE
is high for read cycle.
7CE1
and OE are low and CE2 is high for read cycle.
8 Address valid prior to or coincident with CE1
transition Low.
9 All read cycle timings are referenced from the last valid address to the first transitioning address.
10 N/A
11 All write cycle timings are referenced from the last valid address to the first transitioning address.
12 CE1
and CE2 have identical timing.
13 C = 30 pF, except all high Z and low Z parameters where C = 5 pF.
14 N/A
t
AW
Address
CE1
WE
D
OUT
t
CW1
, t
CW2
t
WP
t
DW
t
DH
t
AH
t
WC
t
AS
CE2
Data valid
D
IN
t
WR
t
WZ
255
Ω
– Output load: see Figure B.
– Input pulse level: GND to 3.0V. See Figure A.
– Input rise and fall times: 2 ns. See Figure A.
– Input and output timing reference levels: 1.5V.
C
13
320
Ω
D
OUT
GND
+3.3V
168
Ω
Thevenin equivalent:
D
OUT
+1.728V
Figure B: 3.3V Output load
10%
90%
10%
90%
GND
+3.0V
Figure A: Input pulse
2 ns