CY7C185
Document #: 38-05043 Rev. *A Page 4 of 11
Switching Characteristics Over the Operating Range
[6]
7C185-15 7C185-20 7C185-25 7C185-35
Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Unit
Read Cycle
t
RC
Read Cycle Time 15 20 25 35 ns
t
AA
Address to Data Valid 15 20 25 35 ns
t
OHA
Data Hold from Address Change 3 5 5 5 ns
t
ACE1
CE
1
LOW to Data Valid 15 20 25 35 ns
t
ACE2
CE
2
HIGH to Data Valid 15 20 25 35 ns
t
DOE
OE LOW to Data Valid 8 9 12 15 ns
t
LZOE
OE LOW to Low Z 3 3 3 3 ns
t
HZOE
OE HIGH to High Z
[7]
7 8 10 10 ns
t
LZCE1
CE
1
LOW to Low Z
[8]
3 5 5 5 ns
t
LZCE2
CE
2
HIGH to Low Z 3 3 3 3 ns
t
HZCE
CE
1
HIGH to High Z
[7, 8]
CE
2
LOW to High Z
7 8 10 10 ns
t
PU
CE
1
LOW to Power-Up
CE
2
to HIGH to Power-Up
0 0 0 0 ns
t
PD
CE
1
HIGH to Power-Down
CE
2
LOW to Power-Down
15 20 20 20 ns
Write Cycle
[9]
t
WC
Write Cycle Time 15 20 25 35 ns
t
SCE1
CE
1
LOW to Write End 12 15 20 20 ns
t
SCE2
CE
2
HIGH to Write End 12 15 20 20 ns
t
AW
Address Set-up to Write End 12 15 20 25 ns
t
HA
Address Hold from Write End 0 0 0 0 ns
t
SA
Address Set-up to Write Start 0 0 0 0 ns
t
PWE
WE Pulse Width 12 15 15 20 ns
t
SD
Data Set-up to Write End 8 10 10 12 ns
t
HD
Data Hold from Write End 0 0 0 0 ns
t
HZWE
WE LOW to High Z
[7]
7 7 7 8 ns
t
LZWE
WE HIGH to Low Z 3 5 5 5 ns
Notes:
6. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 30-pF load capacitance.
7. t
HZOE,
t
HZCE
, and t
HZWE
are specified with C
L
= 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady state voltage.
8. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE1
and t
LZCE2
for any given device.
9. The internal write time of the memory is defined by the overlap of CE
1
LOW, CE
2
HIGH, and WE LOW. All 3 signals must be active to initiate a write and either
signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
