IDT
TM
/ICS
TM
64-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor 1121G—05/19/11
Advance Information
ICS9LPRS501
64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR
16
Table 3: IO_Vout select table
B9b2 B9b1 B9b0 IO_Vout
000
0.3V
001
0.4V
010
0.5V
011
0.6V
100
0.7V
101
0.8V
110
0.9V
111
1.0V
Table 4: Device ID table
000 0
000 1
001 0
001 1
010 0
010 1
011 0
011 1
100 0
100 1
101 0
101 1
110 0
110 1
111 0
111 1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
64 pin TSSOP/QFN
B8b5 B8b4 Comment
56 pin TSSOP/QFN
B8b7 B8b6
IDT
TM
/ICS
TM
64-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor 1121G—05/19/11
Advance Information
ICS9LPRS501
64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR
17
PCI_STOP# Power Management
SMBus OE Bit PCI_STOP# Stop Drive Mode Stoppable Free running Stoppable Free running
1X
Running Running Running Running
0
CK= High
CK# = Low
Running
1
CK= Pull
down
CK# = Low
Running
Disable
XX
CPU_STOP# Power Management
SMBus OE Bit PCI_STOP# Sto
p
Drive Mode Sto
pp
able Free runnin
g
1X
Running Running
0
CK= High
CK# = Low
Running
1
CK= Pull down
CK# = Low
Running
Disable
XX
CR# Power Management
SMBus OE Bit CR# Sto
p
Drive Mode Sto
pp
able Free runnin
g
1
Running Running
0
Disable
X
PD# Power Management
Device State w/o Latched in
p
u
t
w/Latched in
p
u
t
Latches Open
Power Down
M1
Virtual Power Cycle
to Latches Open
Single-ended Clocks
Differential Clocks
(Except CPU)
Low
CK = Pull down, CK# = Low
Differential Clocks
Differential Clocks
Enable
0
Low Low
Enable
0
CK= Pull down, CK# = Low
Low
Enable
CK= Pull down, CK# = Low
X
CK= Pull down, CK# = Low
Low Hi-Z
Single-ended Clocks
CK= Pull down
CK# = Low
CK= Pull down
CK# = Low
CPU1
CK= Pull down, CK# = Low
CK= Pull down, CK# = Low CK= Pull down, CK# = Low
Running
Differential Clocks
(Except CPU1)
CK= Pull down
CK# = Low
IDT
TM
/ICS
TM
64-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor 1121G—05/19/11
Advance Information
ICS9LPRS501
64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR
18
General SMBus serial interface information for the ICS9LPRS501
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2
(H)
ICS clock will
acknowledge
Controller (host) sends the beginning byte location = N
ICS clock will
acknowledge
Controller (host) sends the data byte count = X
ICS clock will
acknowledge
Controller (host) starts sending
Byte N through
Byte N + X -1
ICS clock will
acknowledge
each byte
one at a time
Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit.
Controller (host) sends the write address D2
(H)
ICS clock will
acknowledge
Controller (host) sends the begining byte
location = N
ICS clock will
acknowledge
Controller (host) will send a separate start bit.
Controller (host) sends the read address D3
(H)
ICS clock will
acknowledge
ICS clock will send the data byte count = X
ICS clock sends
Byte N + X -1
ICS clock sends
Byte 0 through byte X (if X
(H)
was written to byte 8)
.
Controller (host) will need to acknowledge each byte
Controller (host) will send a not acknowledge bit
Controller (host) will send a stop bit
ICS (Slave/Receiver)
T
WR
ACK
ACK
ACK
ACK
ACK
P
stoP bit
X Byte
Index Block Write Operation
Slave Address D2
(H)
Beginning Byte = N
WRite
starT bit
Controller (Host)
Byte N + X - 1
Data Byte Count = X
Beginning Byte N
T starT bit
WR WRite
RT Repeat starT
RD ReaD
Beginning Byte N
Byte N + X - 1
N Not acknowledge
PstoP bit
Slave Address D3
(H)
Index Block Read Operation
Slave Address D2
(H)
Beginning Byte = N
ACK
ACK
Data Byte Count = X
ACK
ICS (Slave/Receiver)
Controller (Host)
X Byte
ACK
ACK

9LPRS501SGLFT

Mfr. #:
Manufacturer:
IDT
Description:
Clock Synthesizer / Jitter Cleaner PC MAIN CLOCK
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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