IS31FL3196
Integrated Silicon Solution, Inc. — www.issi.com
Rev. C, 03/21/2017
13
Figure 8 V_BM Signal
CASCADE FOR SYNCHRONIZATION OF CHIPS
Operating in the cascade mode can make two chips
synchronize (Figure 2). By setting the CM bit of
Configuration Register 2 (04h) to “0”, IS31FL3196
operates as a master. There are two pins (CLK, I_AUD)
for synchronization of chips. CLK pin can synchronize
the breathing and I_AUD pin can synchronize the audio
current.
SHUTDOWN MODE
Shutdown mode can either be used as a means of
reducing power consumption or generating a flashing
display (repeatedly entering and leaving shutdown
mode). During shutdown mode all registers retain their
data.
SOFTWARE SHUTDOWN
By setting SSD bit of the Shutdown Register (00h) to
“0”, the IS31FL3196 will operate in software shutdown
mode, wherein they consume only 2A (typ.) current.
When the IS31FL3196 is in software shutdown mode,
all current sources are switched off.
HARDWARE SHUTDOWN
The chip enters hardware shutdown mode when the
SDB pin is pulled low, wherein they consume only 1A
(Typ.) current.
