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LTC1458IG#TRPBF

P1-P3P4-P6P7-P9P10-P12
7
LTC1458/LTC1458L
B11 A
MSB
B11 C
MSB
B0 B
LSB
t
1
t
6
B0 D
LSB
B11 A
CURRENT WORD
t
7
t
2
t
9
t
4
t
3
t
8
CLK
D
IN
D
OUT
CS/LD
t
5
1458 TD
B0 D
PREVIOUS WORD
B11 A
PREVIOUS WORD
B10 A
PREVIOUS WORD
B0 B
PREVIOUS WORD
B11 C
PREVIOUS WORD
B0 D
PREVIOUS WORD
Resolution (n): Resolution is defined as the number of
digital input bits, n. It defines the number of DAC output
states (2
n
) that divide the full-scale range. The resolution
does not imply linearity.
Full-Scale Voltage (V
FS
): This is the output of the DAC
when all bits are set to 1.
Voltage Offset Error (V
OS
): The theoretical voltage at the
output when the DAC is loaded with all zeros. The output
amplifier can have a true negative offset, but because the
part is operated from a single supply, the output cannot go
below zero. If the offset is negative, the output will remain
near 0V resulting in the transfer curve shown in Figure 1.
DAC CODE
1458 F01
OUTPUT
VOLTAGE
NEGATIVE
OFFSET
0V
Figure 1. Effect of Negative Offset
The offset of the part is measured at the code that corre-
sponds to the maximum offset specification:
V
OS
= V
OUT
– [(Code)(V
FS
)/(2
n
– 1)]
Least Significant Bit (LSB): One LSB is the ideal voltage
difference between two successive codes.
LSB = (V
FS
– V
OS
)/(2
n
– 1) = (V
FS
– V
OS
)/4095
Nominal LSBs:
LTC1458 LSB = 4.095V/4095 = 1mV
LTC1458L LSB = 2.5V/4095 = 0.610mV
Integral Nonlinearity (INL): End-point INL is the maxi-
mum deviation from a straight line passing through the
end-points of the DAC transfer curve. Because the part
operates from a single supply and the output cannot go
below zero, the linearity is measured between full scale
and the code corresponding to the maximum offset
specification. The INL error at a given input code is
calculated as follows:
INL = [V
OUT
– V
OS
– (V
FS
– V
OS
)(code/4095)]/LSB
V
OUT
= The output voltage of the DAC measured at
the given input code
TI I G DIAGRA
UWW
DEFI ITIO S
UU
8
LTC1458/LTC1458L
Serial Interface
The data on the D
IN
input is loaded into the shift register
on the rising edge of the clock. Data is loaded as one 48-bit
word, DAC A first, then DAC B, DAC C and DAC D. The MSB
is loaded first for each DAC. The DAC registers load the
data from the shift register when CS/LD is pulled high. The
CLK is disabled internally when CS/LD is high. Note: CLK
must be low before CS/LD is pulled low to avoid an extra
internal clock pulse.
The buffered output of the 48-bit shift register is available
on the D
OUT
pin which swings from ground to V
CC
.
Multiple LTC1458/LTC1458Ls may be daisy-chained to-
gether by connecting the D
OUT
pin to the D
IN
pin of the next
chip, while the CLK and CS/LD signals remain common to
all chips in the daisy-chain. The serial data is clocked to all
of the chips, then the CS/LD signal is pulled high to update
all of them simultaneously.
Reference
The LTC1458L has an internal reference of 1.22V with a full
scale of 2.5V (gain of 2 configuration). The LTC1458
includes an internal 2.048V reference, making 1LSB equal
to 1mV (gain of 2 configuration). When the buffer gain is
2, the external reference must be less than V
CC
/2 and be
capable of driving the 15k minimum DAC resistor ladder.
The external reference must always be less than
V
CC
– 1.5V. The reference output voltage noise spectral
density at 1kHz is 300nV/√Hz.
Voltage Output
The rail-to-rail buffered output of the LTC1458 family can
source or sink 5mA when operating with a 5V supply over
the entire operating temperature range while pulling to
within 300mV of the positive supply voltage or ground.
The output swings to within a few millivolts of either
supply rail when unloaded and has an equivalent output
resistance of 40Ω when driving a load to the rails. The
output can drive 1000pF without going into oscillation.
The output voltage noise spectral density at 1kHz is
600nV/√Hz.
Differential Nonlinearity (DNL): DNL is the difference
between the measured change and the ideal 1LSB change
between any two adjacent codes. The DNL error between
any two codes is calculated as follows:
DNL = (∆V
OUT
– LSB)/LSB
∆V
OUT
= The measured voltage difference between
two adjacent codes
Digital Feedthrough: The glitch that appears at the analog
output caused by AC coupling from the digital inputs when
they change state. The area of the glitch is specified in
(nV)(sec).
DEFI ITIO S
UU
OPERATIO
U
9
LTC1458/LTC1458L
Using Two DACs to Digitally Program the Full Scale
and Offset of a Third
Figure 2 shows how to use one LTC1458 to make a 12-bit
DAC with a digitally programmable full scale and offset.
DAC A and DAC B are used to control the offset and full
scale of DAC C. DAC A is connected in a ×1 configuration
and controls the offset of DAC C by moving REFLO C above
ground. The minimum value to which this offset can be
programmed is 10mV. DAC B is connected in a × 2
configuration and controls the full scale of DAC C by
driving REFHI C. Note that the voltage at REFHI C must be
less than or equal to V
CC
/2, corresponding to DAC B’s code
≤ 2,500 for V
CC
= 5V, since DAC C is being operated in × 2
mode for full rail-to-rail output swing.
The transfer characteristic is:
V
OUTC
= 2 • [D
C
• (2 • D
B
– D
A
) + D
A
] • REFOUT
where REFOUT = The Reference Output
D
A
= (DAC A Digital Code)/4096
This sets the offset.
D
B
= (DAC B Digital Code)/4096
This sets the full scale.
D
C
= (DAC C Digital Code)/4096
V
CC
X1/X2 B
V
OUT B
CLR
REFHI B
GND
REFLO B
REFLO A
REFHI A
REFOUT
NC
V
OUT A
X1/X2 A
V
CC
X1/X2 C
V
OUT C
CS/LD
D
IN
REFHI C
GND
REFLO C
REFLO D
REFHI D
D
OUT
CLK
NC
V
OUT D
X1/X2 D
LTC1458
LTC1458L
0.1µF
V
OUT
5V
1458 F02
500Ω
Figure 2
APPLICATIO S I FOR ATIO
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P1-P3P4-P6P7-P9P10-P12

LTC1458IG#TRPBF

Mfr. #:
Buy LTC1458IG#TRPBF
Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC L/P,Single 5V,Quad 12-Bit Vout DAC
Lifecycle:
New from this manufacturer.
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