Obsolete Product(s) - Obsolete Product(s)
current) is maximum 13mA - over full T - when no
load current is required.
The internal antisaturation circuit allows a drastic
reduction in the current peak which takes place
during the start up.
The reset function supervises the regulator output
voltage inhibiting the microprocessor when the
device is out of regulation and resetting it at the
power-on after a settable delay. The reset is LOW
when the output voltage value is lower than the
reset threshold voltage. At the power-on phase
the output voltage increases (see Fig. 2) and -
when it reaches the power-on V
O
threshold V
RT
(On) - the reset output becomes HIGH after a de-
lay time set by the external capacitor C
d
. At the
power-off the output voltage decreases : at the
V
RT(Off)
threshold value (V
O
-0.15V typ. value) the
reset output instantaneously goes down (LOW
status) inhibiting the microprocessor. The typical
power on-off hysteresis is 50mV.
The three gain stages (operational amplifier,
driver and power PNP) require the external ca-
pacitor (C
omin
= 20
µ
F) to guarantee the global
stability of the system.
Load dump and field decay protections (
±
80V),
reverse voltage (– 18V) and short circuit protec-
tion, thermal shutdown are the main features that
make the L4947PD specially suitable for applica-
tions in the automotive enviroment.
EXTERNAL COMPENSATION
Since the purpose of a voltage regulator is to sup-
ply and load variations, the open loop gain of the
regulator must be very high at low frequencies.
This may cause instability as a result of the vari-
ous poles present in the loop. To avoid this insta-
bility dominant pole compensation is used to re-
duce phase shift due to other poles at the unity
gain frequency. The lower the frequency of these
others poles at the unity gain frequency. The
lower the frequency of these other poles, the
greater must be capacitor esed to create the
dominant pole for the same DC gain.
Where the output transistor is a lateral PNP type
there is a pole in the regulation loop at a fre-
quencybtoo low to be compensated by a capaci-
tor which can be integrated. An external compen-
sation is therefore necessary so a very high value
capacitor must be connected from the output to
ground.
The paeassitic equivalent series resistance of the
capacitor used adds a zero to the regulation loop.
This zero may compromise the stability of the
system since its effect tends to cancel the effect
of the pole added. In regulators this ESR must be
less than 3
Ω
and the minimum capacitor value is
47
µ
F.
Figure 1:
Typical Dropout Voltage vs. T
j
(I
o
= 500mA).
V
rpeak
V
rthys
V
O
V
RT(on)
V
RT(off)
(1) (2)
V
dthh
V
dthl
V
R
V
D
T
d
(2)
V
disch
V
rsat
D94AT109
Figure 2:
Reset Waveforms:
(1) Without External Capacitor C
d
.
(2) With External Capacitor C
d
.
L4947PD
4/6
