© 2002 Fairchild Semiconductor Corporation DS005954 www.fairchildsemi.com
October 1987
Revised March 2002
CD4021BC 8-Stage Static Shift Register
CD4021BC
8-Stage Static Shift Register
General Description
The CD4021BC is an 8-stage parallel input/serial output
shift register. A parallel/serial control input enables individ-
ual JAM inputs to each of 8 stages. Q outputs are available
from the sixth, seventh, and eighth stages. All outputs have
equal source and sink current capabilities and conform to
standard “B” series output drive.
When the parallel/serial control input is in the logical “0”
state, data is serially shifted into the register synchronously
with the positive transition of the clock. When the parallel/
serial control is in the logical “1” state, data is jammed into
each stage of the register asynchronously with the clock.
All inputs are protected against static discharge with diodes
to V
DD
and V
SS
.
Features
■ Wide supply voltage range: 3.0V to 15V
■ High noise immunity: 0.45 V
DD
(typ.)
■ Low power TTL compatibility:
Fan out of 2 driving 74L or 1 driving 74LS
■ 5V–10V–15V parametric ratings
■ Symmetrical output characteristics
■ Maximum input leakage 1
µA at 15V over full tempera-
ture range
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Top View
Truth Table
X = Don't care case
Note 1: Level change
Note 2: No change
Order Number Order Code Package Description
CD4021BCM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
CD4021BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
C
L
(Note 1)
Serial
Input
Parallel/
Serial
Control
PI 1 PI n
Q1
(Internal)
Q
n
(Note 2)
XX1000 0
XX1010 1
XX1101 0
XX1111 1
00XX0Q
n−1
10XX1Q
n−1
X0XXQ1Q
n