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MC74HC368ADTR2G

P1-P3P4-P6P7-P7
© Semiconductor Components Industries, LLC, 2013
June, 2013 − Rev. 2
1 Publication Order Number:
MC74HC368A/D
MC74HC368A
Hex 3-State Inverting
Buffer with Separate 2-Bit
and 4-Bit Sections
High−Performance Silicon−Gate CMOS
The MC74HC368A is identical in pinout to the LS368. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
This device is arranged into 2−bit and 4−bit sections, each having its
own active−low Output Enable. When either of the enables is high, the
affected buffer outputs are placed into high−impedance states. The
HC368A has inverting outputs.
Features
• Output Drive Capability: 15 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 mA
• High Noise Immunity Characteristic of CMOS Devices
• These are Pb−Free Devices
Figure 1. Logic Diagram
3
5
7
9
11
13
2
4
6
10
12
14
OUTPUT ENABLE 1
OUTPUT ENABLE 2
PIN 16 = V
CC
PIN 8 = GND
Y5
Y4
Y3
Y2
Y1
Y0A0
A1
A2
A3
A4
A5
1
15
http://onsemi.com
MARKING
DIAGRAMS
SOIC−16
D SUFFIX
CASE 751B
TSSOP−16
DT SUFFIX
CASE 948F
1
16
1
16
HC368AG
AWLYWW
HC
368A
ALYWG
G
1
16
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G = Pb−Free Package
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
ORDERING INFORMATION
(Note: Microdot may be in either location)
PIN ASSIGNMENT
1
16
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
A4
Y5
A5
OUTPUT
ENABLE 2
V
CC
Y3
A3
Y4
A1
Y0
A0
OUTPUT
ENABLE 1
GND
Y2
A2
Y1
FUNCTION TABLE
Inputs Output
Enable 1,
Enable 2 A Y
LLH
LHL
HXZ
X = don’t care
Z = high−impedance
MC74HC368A
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2
MAXIMUM RATINGS
Symbol Parameter Value Unit
V
CC
DC Supply Voltage (Referenced to GND) −0.5 to + 7.0 V
V
in
DC Input Voltage (Referenced to GND) −0.5 to V
CC
+ 0.5 V
V
out
DC Output Voltage (Referenced to GND) −0.5 to V
CC
+ 0.5 V
I
in
DC Input Current, per Pin ±20 mA
I
out
DC Output Current, per Pin ±25 mA
I
CC
DC Supply Current, V
CC
and GND Pins ±50 mA
P
D
Power Dissipation in Still Air, Plastic DIP†
SOIC Package†
TSSOP Package†
750
500
450
mW
T
stg
Storage Temperature − 65 to + 150 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect device
reliability.
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
V
CC
DC Supply Voltage (Referenced to GND) 2.0 6.0 V
V
in
, V
out
DC Input Voltage, Output Voltage (Referenced to GND) 0 V
CC
V
T
A
Operating Temperature, All Package Types −55 +125 °C
t
r
, t
f
Input Rise and Fall Time V
CC
= 2.0 V
(Figure 2) V
CC
= 4.5 V
V
CC
= 6.0 V
0
0
0
1000
500
400
ns
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
cuit. For proper operation, V
in
and
V
out
should be constrained to the
range GND v (V
in
or V
out
) v V
CC
.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V
CC
).
Unused outputs must be left open.
MC74HC368A
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3
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Symbol
Parameter Test Conditions
V
CC
V
Guaranteed Limit
Unit
− 55 to
25°C
v 85°C v 125°C
V
IH
Minimum High−Level Input
Voltage
V
out
= 0.1 V
|I
out
| v 20 mA
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
IL
Maximum Low−Level Input
Voltage
V
out
= V
CC
− 0.1 V
|I
out
| v 20 mA
2.0
4.5
6.0
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
OH
Minimum High−Level Output
Voltage
V
in
= V
IL
|I
out
| v 20 mA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
in
= V
IL
|I
out
| v 6.0 mA
|I
out
| v 7.8 mA
4.5
6.0
3.98
5.48
3.84
5.34
3.70
5.20
V
OL
Maximum Low−Level Output
Voltage
V
in
= V
IH
|I
out
| v 20 mA
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
in
= V
IH
|I
out
| v 6.0 mA
|I
out
| v 7.8 mA
4.5
6.0
0.26
0.26
0.33
0.33
0.40
0.40
I
in
Maximum Input Leakage Current V
in
= V
CC
or GND 6.0 ± 0.1 ± 1.0 ± 1.0
mA
I
OZ
Maximum Three−State
Leakage Current
Output in High−Impedance State
V
in
= V
IL
or V
IH
V
out
= V
CC
or GND
6.0 ± 0.5 ± 5.0 ± 10
mA
I
CC
Maximum Quiescent Supply
Current (per Package)
V
in
= V
CC
or GND
I
out
= 0 mA
6.0 8 80 160
mA
AC ELECTRICAL CHARACTERISTICS (C
L
= 50 pF, Input t
r
= t
f
= 6 ns)
Symbol
Parameter
V
CC
V
Guaranteed Limit
Unit
− 55 to
25°C
v 85°C v 125°C
t
PLH
,
t
PHL
Maximum Propagation Delay, Input A to Output Y
(Figures 2 and 4)
2.0
4.5
6.0
95
19
16
120
24
20
145
29
25
ns
t
PLZ
,
t
PHZ
Maximum Propagation Delay, Output Enable to Output Y
(Figures 3 and 5)
2.0
4.5
6.0
175
35
30
220
44
37
265
53
45
ns
t
PZL
,
t
PZH
Maximum Propagation Delay, Output Enable to Output Y
(Figures 3 and 5)
2.0
4.5
6.0
190
38
32
240
48
41
285
57
48
ns
t
TLH
,
t
THL
Maximum Output Transition Time, Any Output
(Figures 2 and 4)
2.0
4.5
6.0
60
12
10
75
15
13
90
18
15
ns
C
in
Maximum Input Capacitance − 10 10 10 pF
C
out
Maximum Three−State Output Capacitance (Output in
High−Impedance State
− 15 15 15 pF
C
PD
Power Dissipation Capacitance (Per Buffer)*
Typical @ 25°C, V
CC
= 5.0 V
pF
40
P1-P3P4-P6P7-P7

MC74HC368ADTR2G

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Buffers & Line Drivers IC BUFF/DVR TRI-ST HEX
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