Characteristics TN805, TN815, TS820, TYN608
4/17 DocID7476 Rev 8
Figure 3. Average and DC on-state current
versus ambient temperature
Figure 4. Relative variation of thermal
impedance junction to case versus pulse
duration
I(A)
T(AV)
0,0
0,5
1,0
1,5
2,0
2,5
0 25 50 75 100 125
DPAK
IPAK
TO-220AB
TO-220FPAB
T (°C)
amb
D.C.
α = 180°
Recommended pad layout,
FR4 printed circuit board
1E-3
1E-2 1E-1
1E+0
0.1
0.2
0.5
1.0
K=[Z /R
th(j-c) th(j-c)
]
t (s)
p
Figure 5. Relative variation of thermal
impedance junction to ambient versus pulse
duration
Figure 6. Relative variation of gate trigger
current and holding current versus junction
temperature for TS820
1E-2 1E-1
1E+0
1E+1 1E+2
5E+2
0.01
0.10
1.00
K=[Z /R
th(j-a) th(j-a)
]
t (s)
p
DPAK
TO-220AB / IPAK
TO-220FPAB
Recommended pad layout,
FR4 printed circuit board
-40 -20 0 4020 60 80 100 120 140
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
T (°C)
j
I,I,I[T] /
GTHL j
I ,I ,I [T =25°C]
GTHL j
I
GT
I
H
& I
R = 1k
L
GK
Ω
Figure 7. Relative variation of gate trigger and
holding current versus junction temperature
Figure 8. Relative variation of holding current
versus gate-cathode resistance (typical values)
-40 -20 0 20 40 60 80 100 120 140
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
T (°C)
j
I,I,I[T] /
GT H L j
I ,I ,I [T =25°C]
GT H L j
I
GT
I
H
& I
L
TN8 and TYNx8
1E-2 1E-1 1E+0 1E+1
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
R(k)
GK
Ω
I [R ] / I [ =1k ]
HGK H
ΩR
GK
T
j
= 25°C
TS8
DocID7476 Rev 8 5/17
TN805, TN815, TS820, TYN608 Characteristics
17
Figure 9. Relative variation of dV/dt immunity
versus gate-cathode resistance (typical values)
for TS820
Figure 10. Relative variation of dV/dt immunity
versus gate-cathode capacitance (typical
values) for TS820
0 200 400 600 800 1000 1200 1400 1600 1800 2000
0.01
0.10
1.00
10.00
R(k)
GK
Ω
dV/dt[R ] / dV/dt[ =220 ]
GK
ΩR
GK
T
j
= 125°C
V = 0.67 x V
D DRM
0 20 40 60 80 100 120 140 160 180 200 220
0.0
2.5
5.0
7.5
10.0
12.5
15.0
C (nF)
GK
dV/dt[C ] / dV/dt[ =220 ]
GK
ΩR
GK
T
V = 0.67 x V
= 125°C
R = 220
D DRM
GK
j
Ω
Figure 11. Surge peak on-state current versus
number of cycles
Figure 12. Non-repetitive surge peak on-state
current and corresponding values of I
2
t
0.01 0.10 1.00 10.00
10
100
1000
I (A), I t (A s)
TSM
22
t (ms)
p
I t
2
I
TSM
T initial = 25°C
j
TN8 / TS8
TN8 / TS8
TYN08
TYN08
dI/dt limitation
Sinusoidal pulse width tp < 10 ms
Figure 13. On-state characteristics (maximum
values)
Figure 14. Thermal resistance junction to
ambient versus copper surface under tab
(DPAK)
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
0.1
1.0
10.0
50.0
I (A)
TM
V (V)
TM
T
j
=max
T=25°C
j
V =0.85V
R =46m
T max.:
j
t0
d
Ω
0 2 4 6 8 10 12 14 16 18 20
0
20
40
60
80
100
S(cm²)
R (°C/W)
th(j-a)
Epoxy printed circuit board FR4
copper thickness = 35 µm
Package information TN805, TN815, TS820, TYN608
6/17 DocID7476 Rev 8
2 Package information
Epoxy meets UL94, V0
Lead-free packages
Recommended torque: 0.4 to 0.6 N·m
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK
®
is an ST trademark.
Figure 15. DPAK dimension definitions
Note: this package drawing may slightly differ from the physical package. However, all the
specified dimensions are guaranteed.
D
A1
D1
D
c
c2
H
L4
e1
b
L2
E
b4
E1
A
E1
A2
L
V2

TN815-800B-TR

Mfr. #:
Manufacturer:
STMicroelectronics
Description:
SCRs 8A SCRS
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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