Low Voltage Voice Coil Motor Driver
A3904
5
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
The A3904 output current is controlled by programming the D-to-
A converter value via the I
2
C serial port. The target output current
can be calculated by:
I
OUT
= DAC × 500 μA ,
where DAC = 1 to 255. Code = 0 is a disable state for the output
sink drive. The DAC will be set to code = 0 upon power-up or a
fault condition on V
DD
.
SLEEPZ A logic low input disables all of the internal circuitry
and prevents the IC from draining battery power.
Output Range The voltage on the IOUT pin should be greater
than 500 mV to guarantee the accuracy and linearity of the pro-
grammed current. The output voltage is a function of the battery
voltage, motor resistance, and the programmed load current.
Clamp Diode When the output is turned off, the load induc-
tance causes the output voltage to rise. A clamp diode, from
IOUT to VDD, is integrated in the IC to ensure that the output
voltage remains at a safe level.
I
2
C Interface This is a serial interface that uses two bus lines,
SCL and SDA, to access the internal Control registers. Data is
exchanged between a microcontroller (master) and the A3904
(slave). The clock input to SCL is generated by the master, while
the SDA line functions as either an input or an open drain output,
depending on the direction of the data. The I
2
C input thresholds
do not depend on the V
DD
voltage of the A3904. The levels are
fixed at approximately 1 V. The fixed levels allow the SDA and
SCL lines to be pulled-up to a different logic level than the V
DD
supply of the 3904.
Timing Considerations The control sequence of the com-
munication through the I
2
C interface is composed of several steps
in the following sequence:
1. Start Condition. Defined by a negative edge on the SDA
line, while SCL is high.
2. Address Cycle. 7 bits of address, plus 1 bit to indicate
write (0) or read (1), and an acknowledge bit. The ad-
dress setting is 0x18, 0x1A, 0x1C or 0x1E.
3. Data Cycles. Write 8 bits of data that address the internal
Control register, followed by an acknowledge bit.
4. Stop Condition. Defined by a positive edge on the SDA
line, while SCL is high.
Except to indicate a Start or Stop condition, SDA must be stable
while the clock is high. SDA can only be changed while SCL is
low. It is possible for the Start or Stop condition to occur at any
time during a data transfer. The A3904 always responds by reset-
ting the data transfer sequence.
The Read/Write bit is set low to indicate a write cycle. Multiple
writes are allowed before issuing a Stop condition. There are no
readback functions incorporated into the A3904.
The master monitors for an acknowledge pulse to determine if the
slave device is responding to the address byte sent to the A3904.
When the A3904 decodes the 7-bit address field as a valid
address, it responds by pulling SDA low during the ninth clock
cycle.
During a data write from the master, the A3904 pulls SDA low
during the clock cycle that follows the data byte, in order to indi-
cate that the data has been successfully received.
After sending either an address byte or a data byte, the master
device must release the SDA line before the ninth clock cycle, in
order to allow this handshaking to occur.
Functional Description
