USB2227/USB2228
DS00002256A-page 10 2007-2016 Microchip Technology Inc.
MS_D[3:2] 22
21
I/O8PD MS System Data In/Out:
This pin is a bi-directional data signal for the MS device.
The bi-directional data signal has an internal weak pull-down
resistor.
MS_INS 18 IPU MS Card Insertion:
This pin is the card detection signal from the MS device to
indicate, if the device is inserted.
This pin has an internally controlled weak pull-up resistor.
MS_SCLK 23 O8 MS System CLK:
This pin is an output clock signal to the MS device.
The clock frequency is software configurable.
SD Interface
SD_DAT[3:0] 29
28
27
26
I/O8PU SD Data 3-0:
These are bi-directional data signals.
These pins have internally controlled weak pull-up resistors.
SD_CLK 31 O8 SD Clock:
This is an output clock signal to SD/MMC device.
The clock frequency is software configurable.
SD_CMD 30 I/O8PU SD Command:
This is a bi-directional signal that connects to the CMD signal of
SD/MMC device.
This pin has an internally controlled weak pull-up resistor.
SD_nWP 25 IPD SD Write Protected:
This pin is an input signal with an internal weak pull-down.
This pin has an internally controlled weak pull-down resistor.
USB Interface
USBDM
USBDP
87
88
IO-U USB Bus Data:
These pins connect to the USB bus data signals.
RBIAS 98 I USB Transceiver Bias:
A 12.0k, 1.0% resistor is attached from VSSA to this pin, in
order to set the transceiver’s internal bias currents.
ATEST 99 AIO Analog Test:
This signal is used for testing the analog section of the chip and
should be connected to VDDA33 for normal operation.
VDD18PLL 101 1.8v Power for the PLL
VSSPLL 104 PLL Ground Reference:
Ground Reference for 1.8v PLL power
VDDA33 89 3.3v Analog Power
VSSA 86 Analog Ground Reference:
Analog Ground Reference for 3.3v Analog Power.
Symbol
128-Pin
VTQFP
Buffer Type Description
2007-2016 Microchip Technology Inc. DS00002256A-page 11
USB2227/USB2228
XTAL1/
CLKIN
102 ICLKx Crystal Input/External Clock Input:
24Mhz Crystal or external clock input.
This pin can be connected to one terminal of the crystal or can
be connected to an external 24Mhz clock when a crystal is not
used.
Note: The MA[2:0] pins will be sampled while nRESET is
asserted, and the value will be latched upon nRESET
negation. This will determine the clock source and
value.
XTAL2 103 OCLKx Crystal Output:
24Mhz Crystal
This is the other terminal of the crystal, or left open when an
external clock source is used to drive XTAL1/CLKIN. It may not
be used to drive any external circuitry other than the crystal
circuit.
Memory I/O Interface
MD[7:0] 12
11
10
9
8
7
6
5
I/O8PU Memory Data Bus:
When ROMEN bit of GPIO_IN1 register = 0, these signals are
used to transfer data between the internal CPU and the external
program memory.
These pins have internally controlled weak pull-up resistors.
MA[15:3] 4
2
1
128
127
126
125
124
123
122
121
120
119
O8 Memory Address Bus:
These signals address memory locations within the external
memory.
MA2/
SEL_CLKDRV
118 I/O8PD Memory Address Bus:
MA2 Addresses memory locations within the external memory.
SEL_CLKDRV. During nRESET assertion, this pins will select the
operating clock mode (crystal or externally driven clock source),
and a weak pull-down resistor is enabled. When nRESET is
negated, the value will be internally latched and this pin will revert
to MA2 functionality, the internal pull-down will be disabled.
‘0’ = Crystal operation (24MHz only)
‘1’ = Externally driven clock source (24MHz or 48MHz)
Note: If the latched value is ‘1’, then the MA2 pin is tri-stated
when the following conditions are true:
1. IDLE bit (PCON.0) is 1.
2. INT2 is negated
3. SLEEP bit of CLOCK_SEL is 1.
If the latched value is ‘0’, then the MA2 pin will function identically
to the MA[15:3] pins at all times (other than during nRESET
assertion).
Symbol
128-Pin
VTQFP
Buffer Type Description
USB2227/USB2228
DS00002256A-page 12 2007-2016 Microchip Technology Inc.
MA[1:0]/CLK_SE
L[1:0]
117
116
I/O8PD Memory Address Bus:
MA[1:0], These signals address memory locations within the
external memory.
SEL[1:0]. During nRESET assertion, these pins will select the
operating frequency of the external clock, and the corresponding
weak pull-down resistors are enabled. When nRESET is negated,
the value on these pins will be internal latched and these pins will
revert to MA[1:0] functionality, the internal pull-downs will be
disabled.
SEL[1:0] = ‘00’. 24MHz
SEL[1:0] = ‘01’. RESERVED
SEL[1:0] = ‘10’. RESERVED
SEL[1:0] = ‘11’. 48MHz
Note: If the latched value is ‘1’, then the corresponding MA
pin is tri-stated when the following conditions are true:
1. IDLE bit (PCON.0) is 1.
2. INT2 is negated
3. SLEEP bit of CLOCK_SEL is 1.
If the latched value is ‘0’, then the corresponding MA pin will
function identically to the MA[15:3] pins at all times (other than
during nRESET assertion).
nMWR 14 O8 Memory Write Strobe:
Program Memory Write; active low
nMRD 13 O8 Memory Read Strobe:
Program Memory Read; active low
nMCE 17 O8 Memory Chip Enable:
Program Memory Chip Enable; active low.
This signal is asserted, when any of the following conditions are
no longer met:
1. IDLE bit (PCON.0) is 1.
2. INT2 is negated
3. SLEEP bit of CLOCK_SEL is 1.
Note: This signal is held to a logic ‘high’ while nRESET is
asserted.
MISC
GPIO1 114 I/O8 General Purpose I/O:
This pin may be used either as input, edge sensitive interrupt
input, or output.
GPIO2 113 I/O8 General Purpose I/O:
This pin may be used either as input, edge sensitive interrupt
input, or output.
GPIO3 94 I/O8 General Purpose I/O:
This pin may be used either as input, edge sensitive interrupt
input, or output.
GPIO4 111 I/O8 General Purpose I/O:
This pin may be used either as input, edge sensitive interrupt
input, or output.
Symbol
128-Pin
VTQFP
Buffer Type Description

USB2228-NU-10

Mfr. #:
Manufacturer:
Microchip Technology
Description:
USB Interface IC USB 2.0 Media Card Cntrllr
Lifecycle:
New from this manufacturer.
Delivery:
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