REVISION B 7/20/15
874005 DATA SHEET
9 PCI Express™ Jitter Attenuator
SCHEMATIC EXAMPLE
FIGURE 5. 874005 SCHEMATIC EXAMPLE
DIFFERENTIAL CLOCK INPUT INTERFACE
Figure 5 is an 874005 application example schematic. The
schematic focuses on functional connections and is not con-
fi guration specifi c. Refer to the pin description and functional
tables in the datasheet to ensure that the logic control inputs
are properly set. The input is provided by 3.3V LVPECL
driver with a Y-termination for simplicity, ease of layout and
better control of the termination power over device variations.
As with any high speed analog circuitry, the power supply
pins are vulnerable to random noise. To achieve optimum
jitter performance, power supply isolation is required. The
874005 provides separate VDD and VDDO power supplies
to isolate any high switching noise from coupling into the
internal PLL. In order to achieve the best possible fi ltering, it
is recommended that the placement of the fi lter components
be on the device side of the PCB as close to the power pins
as possible. If space is limited, the 0.1uF capacitor in each
power pin fi lter should be placed on the device side. The
other components can be on the opposite side of the PCB.
Power supply fi lter recommendations are a general guideline
to be used for reducing external noise from coupling into the
devices. The VCC and VCCO fi lters start to attenuate noise at
approximately 10kHz. If a specifi c frequency noise component
is known, such as switching power supplies frequencies, it is
recommended that component values be adjusted and if re-
quired, additional fi ltering be added. Additionally, good gener-
al design practices for power plane voltage stability suggests
adding bulk capacitance in the local area of all devices.
