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874005AGLFT

P1-P3P4-P6P7-P9P10-P12P13-P15
PCI Express™ Jitter Attenuator
874005
DATA SHEET
874005 REVISION B 7/20/15 1 ©2015 Integrated Device Technology, Inc.
GENERAL DESCRIPTION
The 874005 is a high performance Differential-to-LVDS Jitter
Attenuator designed for use in PCI Express systems. In some
PCI Express systems, such as those found in desktop PCs, the
PCI Express clocks are generated from a low bandwidth, high
phase noise PLL frequency synthesizer. In these systems, a jitter
attenuator may be required to attenuate high frequency random
and deterministic jitter components from the PLL synthesizer
and from the system board. The 874005 has 3 PLL bandwidth
modes: 200kHz, 400kHz, and 800kHz. The 200kHz mode will
provide maximum jitter attenuation, but with higher PLL tracking
skew and spread spectrum modulation from the motherboard
synthesizer may be attenuated. The 400kHz provides an
intermediate bandwidth that can easily track triangular spread
profi les, while providing good jitter attenuation. The 800kHz
bandwidth provides the best tracking skew and will pass most
spread profi les, but the jitter attenuation will not be as good
as the lower bandwidth modes. Because some 2.5Gb serdes
have x20 multipliers while others have than x25 multipliers, the
874005 can be set for 1:1 mode or 5/4 multiplication mode (i.e.
100MHz input/125MHz output) using the F_SEL pins.
The 874005 uses IDT’s 3
rd
Generation FemtoClock
®
PLL technology to achive the lowest possible phase noise.
The device is packaged in a 24 Lead TSSOP package, making
it ideal for use in space constrained applications such as PCI
Express add-in cards.
FEATURES
• Five differential LVDS output pairs
• One differential clock input
• CLK and nCLK supports the following input types:
LVPECL, LVDS, LVHSTL, SSTL, HCSL
• Output frequency range: 98MHz - 160MHz
• Input frequency range: 98MHz - 128MHz
• VCO range: 490MHz - 640MHz
• Cycle-to-cycle jitter: 30ps (maximum)
• 3.3V operating supply
• 3 bandwidth modes allow the system designer to make
jitter attenuation/tracking skew design trade-offs
• 0°C to 70°C ambient operating temperature
• Available in lead-free RoHS compliant package
BLOCK DIAGRAM
BW_SEL
0 = PLL Bandwidth: ~200kHz
Float = PLL Bandwidth: ~400kHz (Default)
1 = PLL Bandwidth: ~800kHz
PLL BANDWIDTH
PIN ASSIGNMENT
874005
24-Lead TSSOP
4.40mm x 7.8mm x 0.92mm
package body
G Package
Top View
nQB2
nQA1
QA1
V
DDO
QA0
nQA0
MR
BW_SEL
V
DDA
F_SELA
V
DD
OEA
1
2
3
4
5
6
7
8
9
10
11
12
QB2
V
DDO
QB1
nQB1
QB0
nQB0
F_SELB
OEB
GND
GND
nCLK
CLK
24
23
22
21
20
19
18
17
16
15
14
13
PCI Express™ Jitter Attenuator
874005 DATA SHEET
2 REVISION B 7/20/15
TABLE 1. PIN DESCRIPTIONS
TABLE 2. PIN CHARACTERISTICS
TABLE 3A. OUTPUT ENABLE FUNCTION TABLE
TABLE 3B. PLL BANDWIDTH/PLL BYPASS CONTROL
Inputs Outputs
OEA/OEB QAx/nQAx QBx/nQBx
0 HiZ HiZ
1 Enabled Enabled
Number Name Type Description
1, 24 nQB2, QB2 Output Differential output pair. LVDS interface levels.
2, 3 nQA1, QA1 Output Differential output pair. LVDS interface levels.
4, 23 V
DDO
Power Output supply pins.
5, 6 QA0, nQA0 Output Differential output pair. LVDS interface levels.
7 MR Input Pulldown
Active HIGH Master Reset. When logic HIGH, the internal dividers are
reset causing the true outputs (nQx) to go low and the inverted outputs
(Qx) to go high. When logic LOW, the internal dividers and the outputs
are enabled. LVCMOS/LVTTL interface levels.
8 BW_SEL Input
Pullup/
Pulldown
PLL Bandwidth input. See Table 3B.
9V
DDA
Power Analog supply pin.
10 F_SELA Input Pulldown
Frequency select pin for QAx,nQAx outputs.
LVCMOS/LVTTL interface levels.
11 V
DD
Power Core supply pin.
12 OEA Input Pullup
Output enable pin for QA pins. When HIGH, the QAx/nQAx outputs are
active. When LOW, the QAx,nQAx outputs are in a high impedance state.
LVCMOS/LVTTL interface levels.
13 CLK Input Pulldown Non-inverting differential clock input.
14 nCLK Input Pullup Inverting differential clock input.
15, 16 GND Power Power supply ground.
17 OEB Input Pullup
Output enable pin for QB pins. When HIGH, the QBx/nQBx outputs are
active. When LOW, the QBx,nQBx outputs are in a high impedance state.
LVCMOS/LVTTL interface levels.
18 F_SELB Input Pulldown
Frequency select pin for QBx,nQBx outputs.
LVCMOS/LVTTL interface levels.
19, 20 nQB0, QB0 Output Differential output pair. LVDS interface levels.
21, 22 nQB1, QB1 Output Differential output pair. LVDS interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance 4 pF
R
PULLUP
Input Pullup Resistor 51 kΩ
R
PULLDOWN
Input Pulldown Resistor 51
kΩ
Inputs
PLL Band-
width
PLL_BW
0 ~200kHz
1 ~800kHz
Float ~400kHz
REVISION B 7/20/15
874005 DATA SHEET
3 PCI Express™ Jitter Attenuator
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, V
DD
= V
DDA
= V
DDO
= 3.3V±5%, TA = 0°C TO 70°C
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5 V
Outputs, V
O
-0.5V to V
DDO
+ 0.5V
Package Thermal Impedance, θ
JA
70°C/W (0 lfpm)
Storage Temperature, T
STG
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifi cations only. Functional
operation of product at these conditions or any conditions
beyond those listed in the DC Characteristics or AC Charac-
teristics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, V
DD
= V
DDA
= V
DDO
= 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
DD
Core Supply Voltage 3.135 3.3 3.465 V
V
DDA
Analog Supply Voltage 3.135 3.3 3.465 V
V
DDO
Output Supply Voltage 3.135 3.3 3.465 V
I
DD
Power Supply Current 85 mA
I
DDA
Analog Supply Current 15 mA
I
DDO
Output Supply Current 115 mA
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
IH
Input High Voltage
OEA, OEB, MR,
F_SELA, F_SELB
2V
DD
+ 0.3 V
BW_SEL V
DD
- 0.4 V
V
IL
Input Low Voltage
OEA, OEB, MR,
F_SELA, F_SELB
-0.3 0.8 V
BW_SEL 0.4 V
V
IM
Input Mid Voltage BW_SEL V
DD
/2 - 0.1 V
DD
/2 + 0.1 V
I
IH
Input High Current
OEA, OEB V
DD
= V
IN
= 3.465V 5 µA
F_SELA, F_SELB
MR, BW_SEL
V
DD
= V
IN
= 3.465V 150 µA
I
IL
Input Low Current
BW_SEL,
OEA, OEB
V
DD
= 3.465V, V
IN
= 0V -150 µA
MR,
F_SELA, F_SELB
V
DD
= 3.465V, V
IN
= 0V -5 µA
P1-P3P4-P6P7-P9P10-P12P13-P15

874005AGLFT

Mfr. #:
Buy 874005AGLFT
Manufacturer:
IDT
Description:
Clock Synthesizer / Jitter Cleaner PCI EXPRESS JITTER ATTENUATOR
Lifecycle:
New from this manufacturer.
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