5-146305-4 Datasheet AT91M40800-33AU, AT91M40800-33AU-999, 5-146305-4 | P7-P9

1348FS–ATARM–13-Apr-06

AT91M40800

7. Product Overview

7.1 Power Supply

The AT91M40800 microcontroller has a unique type of power supply pin – VDD. The VDD pin

supplies the I/O pads and the device core. The supported voltage range on V

is 1.8V to 3.6V.

7.2 Input/Output Considerations

The AT91M40800 microcontroller I/O pads are 5V-tolerant, enabling them to interface with

external 5V devices without any additional components. Thus, the devices accept 5V (3V) on the

inputs even if powered at 3V (2V). For further information, refer to the “AT91M40800 Electrical

Characteristics” datasheet.

After the reset, the peripheral I/Os are initialized as inputs to provide the user with maximum

flexibility. It is recommended that in any application phase, the inputs to the AT91M40800 micro-

controller be held at valid logic levels to minimize the power consumption.

7.3 Master Clock

The AT91M40800 microcontroller has a fully static design and works on the Master Clock

(MCK), provided on the MCKI pin from an external source.

The Master Clock is also provided as an output of the device on the pin MCKO, which is multi-

plexed with a general-purpose I/O line. While NRST is active, MCKO remains low. After the

reset, the MCKO is valid and outputs an image of the MCK signal. The PIO controller must be

programmed to use this pin as standard I/O line.

7.4 Reset

Reset restores the default states of the user interface registers (defined in the user interface of

each peripheral), and forces the ARM7TDMI to perform the next instruction fetch from address

zero. Except for the program counter the ARM7TDMI registers do not have defined reset states.

7.4.1 NRST Pin

NRST is active low-level input. It is asserted asynchronously, but exit from reset is synchronized

internally to the MCK. The signal presented on MCKI must be active within the specification for a

minimum of 10 clock cycles up to the rising edge of NRST, to ensure correct operation.

The first processor fetch occurs 80 clock cycles after the rising edge of NRST.

7.4.2 Watchdog Reset

The watchdog can be programmed to generate an internal reset. In this case, the reset has the

same effect as the NRST pin assertion, but the pins BMS and NTRI are not sampled. Boot Mode

and Tri-state Mode are not updated. If the NRST pin is asserted and the watchdog triggers the

internal reset, the NRST pin has priority.

7.5 Emulation Functions

7.5.1 Tri-state Mode

The AT91M40800 microcontroller provides a Tri-state mode, which is used for debug purposes.

This enables the connection of an emulator probe to an application board without having to des-

older the device from the target board. In Tri-state mode, all the output pin drivers of the

AT91M40800 microcontroller is disabled.

1348FS–ATARM–13-Apr-06

AT91M40800

To enter Tri-state mode, the pin NTRI must be held low during the last 10 clock cycles before the

rising edge of NRST. For normal operation the pin NTRI must be held high during reset by a

resistor of up to 400K Ohm.

NTRI is multiplexed with I/O line P21 and USART1 serial data transmit line TXD1.

Standard RS232 drivers generally contain internal 400K Ohm pull-up resistors. If TXD1 is con-

nected to a device not including this pull-up, the user must make sure that a high level is tied on

NTRI while NRST is asserted.

7.5.2 JTAG/ICE Debug

ARM Standard Embedded In-circuit Emulation is supported via the JTAG/ICE port. The pins

TDI, TDO, TCK and TMS are dedicated to this debug function and can be connected to a host

computer via the external ICE interface.

In ICE Debug mode, the ARM7TDMI core responds with a non-JTAG chip ID that identifies the

microcontroller. This is not fully IEEE

1149.1 compliant.

7.6 Memory Controller

The ARM7TDMI processor address space is 4G bytes. The memory controller decodes the

internal 32-bit address bus and defines three address spaces:

• Internal memories in the four lowest megabytes

• Middle space reserved for the external devices (memory or peripherals) controlled by the EBI

• Internal peripherals in the four highest megabytes

In any of these address spaces, the ARM7TDMI operates in Little-Endian mode only.

7.6.1 Internal Memories

The AT91M40800 microcontroller integrates 8K bytes of internal SRAM. All internal memories

are 32 bits wide and single-clock cycle accessible. Byte (8-bit), half-word (16-bit) or word (32-bit)

accesses are supported and are executed within one cycle. Fetching Thumb or ARM instruc-

tions is supported and internal memory can store twice as many Thumb instructions as ARM

ones.

The SRAM is mapped at address 0x0 (after the remap command), allowing ARM7TDMI excep-

tion vectors between 0x0 and 0x20 to be modified by the software. The rest of the bank can be

used for stack allocation (to speed up context saving and restoring) or as data and program stor-

age for critical algorithms.

7.6.2 Boot Mode Select

The ARM reset vector is at address 0x0. After the NRST line is released, the ARM7TDMI exe-

cutes the instruction stored at this address. This means that this address must be mapped in

nonvolatile memory after the reset.

The input level on the BMS pin during the last 10 clock cycles before the rising edge of the

NRST selects the type of boot memory (see Table 7-1).

1348FS–ATARM–13-Apr-06

AT91M40800

The pin BMS is multiplexed with the I/O line P24 that can be programmed after reset like any

standard PIO line.

7.6.3 Remap Command

The ARM vectors (Reset, Abort, Data Abort, Prefetch Abort, Undefined Instruction, Interrupt,

Fast Interrupt) are mapped from address 0x0 to address 0x20. In order to allow these vectors to

be redefined dynamically by the software, the AT91M40800 microcontroller uses a remap com-

mand that enables switching between the boot memory and the internal primary SRAM bank

addresses. The remap command is accessible through the EBI User Interface, by writing one in

RCB of EBI_RCR (Remap Control Register). Performing a remap command is mandatory if

access to the other external devices (connected to chip-selects 1 to 7) is required. The remap

operation can only be changed back by an internal reset or an NRST assertion.

7.6.4 Abort Control

The abort signal providing a Data Abort or a Prefetch Abort exception to the ARM7TDMI is

asserted when accessing an undefined address in the EBI address space.

No abort is generated when reading the internal memory or by accessing the internal peripher-

als, whether the address is defined or not.

7.6.5 External Bus Interface

The External Bus Interface handles the accesses between addresses 0x0040 0000 and 0xFFC0

0000. It generates the signals that control access to the external devices, and can be configured

from eight 1-Mbyte banks up to four 16-Mbyte banks. It supports byte-, half-word- and word-

aligned accesses.

For each of these banks, the user can program:

• Number of wait states

• Number of data float times (wait time after the access is finished to prevent any bus

contention in case the device is too long in releasing the bus)

• Data bus-width (8-bit or 16-bit).

• With a 16-bit wide data bus, the user can program the EBI to control one 16-bit device (Byte

Access Select mode) or two 8-bit devices in parallel that emulate a 16-bit memory (Byte

Write Access mode).

The External Bus Interface features also the Early Read Protocol, configurable for all the

devices, that significantly reduces access time requirements on an external device in the case of

single-clock cycle access.

Table 7-1. Boot Mode Select

BMS Boot Memory

1 External 8-bit memory on NCS0

0 External 16-bit memory on NCS0

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18

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