Philips Semiconductors Product data
PCK111
Low voltage 1:10 differential
ECL/PECL/HSTL clock driver
2
2004 Apr 23
FEATURES
• 85 ps part-to-part skew typical
• 20 ps output-to-output skew typical
• Differential design
• V
BB
output
• Low voltage V
EE
range of –2.25 V to –3.8 V for ECL
• Low voltage V
CC
range of +2.375 V to +3.8 V for PECL
• 75 kΩ input pull-down resistors
• ECL/PECL outputs
• Form, fit, and function compatible with MC100EP111
DESCRIPTION
The PCK111 is a low skew 1-to-10 differential driver, designed with
clock distribution in mind. It accepts two clock sources into an input
multiplexer. The PECL input signals can be either differential or
single-ended if the V
BB
output is used. The selected signal is fanned
out to 10 identical differential outputs.
The PCK111 is specifically designed, modeled and produced with
low skew as the key goal. Optimal design and layout serve to
minimize gate-to-gate skew within a device, and empirical modeling
is used to determine process control limits that ensure consistent
t
PD
distributions from lot to lot. The net result is a dependable,
guaranteed low skew device.
To ensure that the tight skew specification is met, it is necessary that
both sides of the differential output are terminated into 50 Ω, even if
only one side is being used. In most applications, all ten differential
pairs will be used, and therefore terminated. In the case where fewer
than ten pairs are used, it is necessary to terminate at least the
output pairs on the same package side as the pair(s) being used on
that side, in order to maintain minimum skew. Failure to do this will
result in small degradations of propagation delay (on the order of
10–20 ps) of the output(s) being used, which, while not being
catastrophic to most designs, will mean a loss of skew margin.
The PCK111 can be used for high performance clock distribution in
+3.3 V or +2.5 V systems. Designers can take advantage of the
PCK111’s performance to distribute low skew clocks across the
backplane or the board. In a PECL environment, series or Thevenin
line terminations are typically used as they require no additional
power supplies.
The PCK111 may be driven single-endedly utilizing the V
BB
bias
output with the CLK0
input. If a single-ended signal is to be used,
the V
BB
pin should be connected to the CLK0 input and bypassed to
ground via a 0.01 µF capacitor. The V
BB
output can only source/sink
0.2 mA, therefore, it should be used as a switching reference for the
PCK111 only. Part-to-part skew specifications are not guaranteed
when driving the PCK111 single-endedly.
PINNING
Pin configurations
V
BB
24
23
22
21
20
19
18
17
9
10
11
12
13
14
15
16
Q3
Q3
Q4
Q4
Q5
Q5
Q6
Q6
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
PCK111BD
SW00907
V
Q9
Q9
Q8
Q8
Q7
Q7
CLK_SEL
CLK0
CLK0
CLK1
CLK1
Q0
Q0
Q1
Q1
Q2
Q2
V
EE
V
CC
CCO
V
CCO
V
CCO
V
CCO
Figure 1. LQFP32 pin configuration
PCK111BS
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
V
CC
V
CCO
CLK_SEL
CLK0
CLK0
CLK1
CLK1
V
BB
V
EE
Q9
Q9
Q8
Q8
Q7
Q7
V
CCO
Q3
Q3
Q4
Q4
Q5
Q5
Q6
Q6
V
CCO
V
CCO
Q0
Q0
Q1
Q1
Q2
Q2
SW02236
Figure 2. HVQFN32 pin configuration
ORDERING INFORMATION
Package
Temperature
u
Name Description Version
range
PCK111BD LQFP32 plastic low profile quad flat package; 32 leads; body 7 × 7 × 1.4 mm SOT358-1 –40 °C to +85 °C
PCK111BS HVQFN32
plastic thermal enhanced very thin quad flat package; no leads;
32 terminals; body 5 × 5 × 0.85 mm
SOT617-1 –40 °C to +85 °C
