9397 750 13276 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet Rev. 03 — 11 May 2004 4 of 20
Philips Semiconductors
74LVC821A
10-bit D-type flip-flop with 5 V tolerant inputs/outputs
Fig 4. Logic diagram.
001aaa681
Q4
D4
Q3
D3
Q2
D2
Q1
D1
Q0
D0
D
FF1
Q
CP
CP
D
FF2
Q
CP
D
FF3
Q
CP
D
FF4
Q
CP
D
FF5
Q
CP
D
FF6
Q
CP
D
FF7
Q
CP
D
FF10
Q
CP
OE
Q5
D5
Q6
D6
Q9
D9
D
FF8
Q
CP
D
FF9
Q
CP
Q7
D7
Q8
D8
9397 750 13276 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet Rev. 03 — 11 May 2004 5 of 20
Philips Semiconductors
74LVC821A
10-bit D-type flip-flop with 5 V tolerant inputs/outputs
6. Pinning information
6.1 Pinning
6.2 Pin description
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as
a supply pin or input.
Fig 5. Pin configuration SO24 and (T)SSOP24. Fig 6. Pin configuration DHVQFN24.
821A
OE
V
CC
D0 Q0
D1 Q1
D2 Q2
D3 Q3
D4 Q4
D5 Q5
D6 Q6
D7 Q7
D8 Q8
D9 Q9
GND CP
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1
2
3
4
5
6
7
8
9
10
11
12
14
13
16
15
18
17
20
19
22
21
24
23
1
2
3
4
5
6
7
8
9
D0
D1
D2
D3
D4
D5
D6
D7
23
22
21
20
19
18
17
16
Q1
Q0
Q2
Q3
Q4
Q5
Q6
Q7
10
11
D8
D9
15
14
Q8
Q9
24
OE
V
CC
12 13
GND
Top view
CP
GND
(1)
001aaa680
Table 3: Pin description
Symbol Pin Description
OE 1 output enable input (active LOW)
D0 2 data input
D1 3 data input
D2 4 data input
D3 5 data input
D4 6 data input
D5 7 data input
D6 8 data input
D7 9 data input
D8 10 data input
D9 11 data input
9397 750 13276 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet Rev. 03 — 11 May 2004 6 of 20
Philips Semiconductors
74LVC821A
10-bit D-type flip-flop with 5 V tolerant inputs/outputs
7. Functional description
[1] H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition;
Z = high-impedance OFF-state;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition;
NC = no change;
X = don’t care.
8. Limiting values
GND 12 ground (0 V)
CP 13 clock input (LOW-to-HIGH, edge-triggered)
Q9 14 3-state flip-flop output
Q8 15 3-state flip-flop output
Q7 16 3-state flip-flop output
Q6 17 3-state flip-flop output
Q5 18 3-state flip-flop output
Q4 19 3-state flip-flop output
Q3 20 3-state flip-flop output
Q2 21 3-state flip-flop output
Q1 22 3-state flip-flop output
Q0 23 3-state flip-flop output
V
CC
24 supply voltage
Table 3: Pin description
…continued
Symbol Pin Description
Table 4: Function table
[1]
Operating mode Input Internal
flip-flops
Output
OE CP Dn Qn
Load and read register L ILL
L hHH
Load register and disable outputs H ILZ
H hHZ
Hold L H or L X NC NC
Table 5: Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to
GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
V
CC
supply voltage 0.5 +6.5 V
I
IK
input diode current V
I
<0 V - 50 mA
V
I
input voltage
[1]
0.5 +6.5 V
I
OK
output diode current V
O
>V
CC
or V
O
<0 V - ±50 mA

74LVC821ADB,118

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
Flip Flops 10-BIT INTERFACE
Lifecycle:
New from this manufacturer.
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