Characteristics SMP100LC
4/13 Doc ID 7050 Rev 14
Table 4. Electrical characteristics - values (T
amb
= 25 °C)
Order code
I
RM
@ V
RM
I
R
@ V
R
Dynamic
V
BO
(1)
1. See Figure 16: Test circuit 1 for Dynamic I
BO
and V
BO
parameters
Static
V
BO
@ I
BO
(2)
2. See Figure 17: Test circuit 2 for I
BO
and V
BO
parameters
I
H
(3)
3. See Figure 18: Test circuit 3 for dynamic I
H
parameter
C
(4)
4. V
R
= 50 V bias, V
RMS
=1 V, F = 1 MHz
C
(5)
5. V
R
= 2V bias, V
RMS
=1 V, F = 1 MHz
max. max. max. max. max. min. typ. typ.
µA V µA V V V mA mA pF pF
SMP100LC-8
2
6
5
82515
800
50
(typ.)
NA 75
SMP100LC-25 22 25 40 35
150
NA 65
SMP100LC-35 32 35 55 55 NA 55
SMP100LC-65 55 65 85 85 45 90
SMP100LC-90 81 90 120 125 40 80
SMP100LC-120 108 120 155 150 35 75
SMP100LC-140 126 140 180 175 30 65
SMP100LC-160 144 160 205 200 30 65
SMP100LC-200 180 200 255 250 30 60
SMP100LC-230 207 230 295 285 30 60
SMP100LC-270 243 270 345 335 30 60
SMP100LC-320 290 320 400 390 25 50
SMP100LC-360 325 360 460 450 25 50
SMP100LC-400 360 400 540 530 20 45
SMP100LC Characteristics
Doc ID 7050 Rev 14 5/13
Figure 2. Pulse waveform Figure 3. Non repetitive surge peak on-state
current versus overload duration
100
50
%I
PP
t
r
t
p
0
t
Repetitive peak pulse current
tr = rise time (µs)
tp = pulse duration time (µs)
I (A)
TSM
1E-2 1E-1 1E+0 1E+1 1E+2 1E+3
0
10
20
30
40
50
60
70
F=50Hz
T initial = 25°C
j
t(s)
Figure 4. On-state voltage versus on-state
current (typical values)
Figure 5. Relative variation of holding
current versus junction
temperature
10
100
012345678
V (V)
T
I (A)
T
T initial = 25°C
j
I [T ] / I [T =25°C]
HH
jj
-25 0 25 50 75 100 125
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
T (°C)
j
Figure 6. Relative variation of breakover
voltage versus junction
temperature
Figure 7. Relative variation of leakage
current versus junction
temperature (typical values)
-25 0 25 50 75 100 125
0.96
0.98
1.00
1.02
1.04
1.06
1.08
V [ ] / V [ =25°C]
BO BO
TT
jj
T (°C)
j
I [ ] / I [ =25°C]
RR
TT
jj
25 50 75 100 125
1
10
100
1000
2000
T (°C)
j
Application information SMP100LC
6/13 Doc ID 7050 Rev 14
2 Application information
In wire line applications, analog or digital, both central office and subscriber sides have to be
protected. This function is assumed by a combined series / parallel protection stage.
Figure 10. Examples of protection stages for line cards
In such a stage, parallel function is assumed by one or several Trisil, and is used to protect
against short duration surge (lightning). During this kind of surges the Trisil limits the voltage
across the device to be protected at its break over value and then fires. The fuse assumes
the series function, and is used to protect the module against long duration or very high
current mains disturbances (50/60Hz). It acts by safe circuit opening. Lightning surge and
mains disturbance surges are defined by standards like GR1089, TIA/EIA IS-968,
ITU-T K20.
Figure 11. Typical circuits
Figure 8. Variation of thermal impedance
junction to ambient versus pulse
duration
Figure 9. Relative variation of junction
capacitance versus reverse voltage
applied (typical values)
1E-3 1E-2 1E-1 1E+0 1E+1 1E+2 5E+2
0.01
0.1
1
t (s)
p
Z/R
th(j-a) th(j-a)
Printed circuit board - FR4,
copper thickness = 35µm,
recommended pad layout
C [V ] / C [V =2V]
RR
12
5 10 20 50 100 300
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
V (V)
R
F =1MHz
V = 1V
T = 25°C
j
RMS
Line
Protection stage
Protection stage
Ring
relay
Line
Ex. Analog line card Ex. xDSL line card or terminal
Fuse TCP 1.25A
T1
T2
SMP100LC-xxx
Typical circuit for subscriber side
Fuse TCP 1.25A
Tip S
Gnd
SMP100LC-xxx
Ring S
SMP100LC-xxx
Fuse TCP 1.25A
Tip L
Gnd
Ring L
Typical circuit for central office side

SMP100LC-160

Mfr. #:
Manufacturer:
STMicroelectronics
Description:
Surge Suppressors 160V 50uA Bidirect
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union