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USB2534-1080AEN-TR

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P52
USB 2.0 Hi-Speed 4-Port Hub Controller
Datasheet
2014 Microchip Technology Inc. DS00001713A-page 37
8.2 Flex Connect
This feature allows the upstream port to be swapped with downstream physical port 1. Only
downstream port 1 can be swapped physically. Using port remapping, any logical port (number
assignment) can be swapped with the upstream port (non-physical).
Flex Connect is enabled/disabled via two control bits in the Connect Configuration Register. The
FLEXCONNECT configuration bit switches the port, and EN_FLEX_MODE enables the mode.
8.2.1 Port Control
Once EN_FLEX_MODE bit is set, the functions of certain pins change, as outlined below.
If EN_FLEX_MODE is set and FLEXCONNECT is not set:
1. PRTPWR1 enters combined mode, becoming PRTPWR1/OCS1_N
2. OCS1_N becomes a don’t care
3. SUSPEND outputs ‘0’ to keep any upstream power controller off
If EN_FLEX_MODE is set and FLEXCONNECT is
set:
1. The normal upstream VBUS pin becomes a don’t care
2. PRTPWR1 is forced to a ‘1’ in combined mode, keeping the port power on to the application
processor.
3. OCS1 becomes VBUS from the application processor through a GPIO
4. SUSPEND becomes PRTPWR1/OCS1_N for the port power controller for the connector port
8.3 Resets
The device has the following chip level reset sources:
Power-On Reset (POR)
External Chip Reset (RESET_N)
USB Bus Reset
8.3.1 Power-On Reset (POR)
A power-on reset occurs whenever power is initially supplied to the device, or if power is removed and
reapplied to the device. A timer within the device will assert the internal reset per the specifications
listed in Section 9.5.1, "Power-On Configuration Strap Valid Timing," on page 45.
8.3.2 External Chip Reset (RESET_N)
A valid hardware reset is defined as assertion of RESET_N, after all power supplies are within
operating range, per the specifications in Section 9.5.2, "Reset and Configuration Strap Timing," on
page 46. While reset is asserted, the device (and its associated external circuitry) enters Standby Mode
and consumes minimal current.
Assertion of RESET_N causes the following:
1. The PHY is disabled and the differential pairs will be in a high-impedance state.
2. All transactions immediately terminate; no states are saved.
3. All internal registers return to the default state.
USB 2.0 Hi-Speed 4-Port Hub Controller
Datasheet
DS00001713A-page 38
2014 Microchip Technology Inc.
4. The external crystal oscillator is halted.
5. The PLL is halted.
Note: All power supplies must have reached the operating levels mandated in Section 9.2, "Operating
Conditions**," on page 42, prior to (or coincident with) the assertion of RESET_N.
8.3.3 USB Bus Reset
In response to the upstream port signaling a reset to the device, the device performs the following:
Note: The device does not propagate the upstream USB reset to downstream devices.
1. Sets default address to 0.
2. Sets configuration to: Unconfigured.
3. Moves device from suspended to active (if suspended).
4. Complies with Section 11.10 of the USB 2.0 Specification for behavior after completion of the
reset sequence.
The host then configures the device in accordance with the USB Specification.
8.4 Link Power Management (LPM)
The device supports the L0 (On), L1 (Sleep), and L2 (Suspend) link power management states per
the USB 2.0 Link Power Management Addendum. These supported LPM states offer low transitional
latencies in the tens of microseconds versus the much longer latencies of the traditional USB
suspend/resume in the tens of milliseconds. The supported LPM states are detailed in Table 8.3. For
additional information, refer to the USB 2.0 Link Power Management Addendum.
Note: State change timing is approximate and is measured by change in power consumption.
Note: System clocks are stopped only in suspend mode or when power is removed from the device.
8.5 Remote Wakeup Indicator (SUSP_IND)
The remote wakeup indicator feature uses the SUSP_IND as a side band signal to wake up the host
when in suspend. This feature is enabled and disabled via the HUB_RESUME_INHIBIT configuration
bit in the hub configuration space register CFG3. The only way to control the bit is by configuration
EEPROM, SMBus or internal ROM default setting. The state is only modified during a power on reset,
or hardware reset. No dynamic reconfiguring of this capability is possible.
Table 8.3 LPM State Definitions
STATE DESCRIPTION ENTRY/EXIT TIME TO L0
L2 Suspend Entry: ~3 ms
Exit: ~2 ms
L1 Sleep Entry: ~65 us
Exit: ~100 us
L0 Fully Enabled (On) -
USB 2.0 Hi-Speed 4-Port Hub Controller
Datasheet
2014 Microchip Technology Inc. DS00001713A-page 39
When HUB_RESUME_INHIBIT = ‘0’, Normal Resume Behavior per the USB 2.0 specification
When HUB_RESUME_INHIBIT = ‘1’, Modified Resume Behavior is enabled
Refer to the following subsections for additional details.
8.5.1 Normal Resume Behavior
VBUS_DET is used to detect presence of the Host. If VBUS_DET = ‘1’, then D+ pull-up is asserted
and normal USB functionality is enabled. The SUSP_IND provides an indication of the active or
suspended state of the hub.
The Hub will drive a ‘K’ on the upstream port if required to do so by USB protocol.
If VBUS_DET = ‘0’, then the D+ pull-up is negated. If battery charging is not enabled, the internal hub
logic will be reset, thus negating all downstream ports and associated downstream VBUS enable
signals. The hub will need to be re-enumerated to function, much like a new connect or after a
complete system reset.
8.5.2 Modified Resume Behavior
When the modified resume feature is enabled, the hub functions as follows:
VBUS_DET is used to detect presence of the Host. If VBUS_DET = ‘1’, then D+ pull-up is asserted
and normal USB functionality is enabled. SUSP_IND provides an indication of the active or suspended
state of the hub.
The device will drive a ‘K’ on the upstream port and downstream ports if required to do so by USB
protocol. The device will act as a controlling hub if required to do so by the USB protocol.
If VBUS_DET = ‘0’, then the D+ pull-up is negated, but the hub will not be internally reset. It will power-
on the downstream ports. The hub is able to continue to detect downstream remote wake events.
SUSP_IND provides an indication of the active or suspended state of the hub.
If a USB 2.0 specification compliant resume or wake event is detected by the device, the device is
remote wake enabled, and a port status change event occurs, SUSP_IND will be driven for the time
given in the GLOBAL_RESUME_TIME register.
If a remote wake event is detected on a downstream port:
1. Device disconnect
2. Device connect
3. A currently connected device requests remote wake-up.
Note: Downstream resume events are filtered for approximately 100uS by internal logic.
The device will not drive a ‘K’ on the upstream port. Instead, the SUSP_IND will be driven for
approximately 14 ms. The ‘K’ is not driven upstream because this would potentially back drive a
powered-down host. The device will drive RESUME to only the downstream ports which transmitted
the remote wake signal per the requirements of the USB 2.0 specification for controlling hub behavior.
Note: SUSP_IND is a one shot event. It will assert with each wake event detection. It will not
repeatedly assert in proxy for downstream devices.
For the case where the Host responds and turns on VBUS and can drive a ‘K’ downstream within the
14 ms time frame of a standard resume (measured from the SUSP_IND pin), then the hub detects the
‘K’. It will discontinue “Controlling Hub” activities, drive resume signaling on any other ports, and
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P52

USB2534-1080AEN-TR

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Buy USB2534-1080AEN-TR
Manufacturer:
Microchip Technology
Description:
USB Interface IC 4-pt USB2.0 Hub Cntlr
Lifecycle:
New from this manufacturer.
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