SDRAM data path widths of 8, 16, 32, 64 and 72 bits
Variable address widths for different memory devices
Programmable timing parameters
Byte level writing through Data Mask signals
Burst termination
The DDR2 SDRAM Controller - Pipelined is available as an IPexpress user configurable IP core, which allows the
configuration of the IP and generation of a netlist and simulation file for use in designs. Please note that generating a
bitstream may be prevented or the bitstream may have time logic present unless a license for the IP is purchased.
Performance and Resource Utilization
Parameter Settings
2
SLICEs LUTs Registers I/O
f
MAX
(MHz)
3
User Guide Table 3-1 parameter defaults 1189 1386 1567 258 266 MHz (533 DDR2)
LatticeECP3
1
1. Performance and utilization characteristics are generated using LFE3-95E-8FN1156CES with Lattice ispLEVER 8.1 software in DDR2
mode. Performance may vary when using this IP core in a different density, speed or grade within the LatticeECP3 family.
2. SDRAM data path width of 32 bits.
3. The DDR2 IP core can operate at 266 MHz (533 DDR2) in the fastest speed-grade (-8) when the data width is 64 bits or less and 2 or
fewer chip selects are used. For help with designs running at 266 MHz, contact your local sales office.
Parameter Settings
2
SLICEs LUTs Registers I/O
f
MAX
(MHz)
3
User Guide Table 3-1 parameter defaults 1234 1435 1530 258 266 MHz (533 DDR2)
LatticeECP2M/S
1
1. Performance and utilization characteristics are generated using LFECP2M-35E-6F672C with Lattice ispLEVER 8.1 software in DDR2
mode. Performance may vary when using this IP core in a different density, speed or grade within the LatticeECP2M/S family.
2. SDRAM data path width of 32 bits.
3. The DDR2 IP core can operate at 266 MHz (533 DDR2) in the fastest speed-grade (-7) when the data width is 64 bits or less and 2 or
fewer chip selects are used. For help with designs running at 266 MHz, contact your local sales office.
Parameter Settings
2
SLICEs LUTs Registers I/O
f
MAX
(MHz)
3
User Guide Table 3-1 parameter defaults 1234 1435 1530 258 266 MHz (533 DDR2)
LatticeECP2/S
1
1. Performance and utilization characteristics are generated using LFECP2-50E-6F672C Lattice ispLEVER 8.1 software in DDR2 mode.
Performance may vary when using this IP core in a different density, speed or grade within the LatticeECP2/S family.
2. SDRAM data path width of 32 bits.
3. The DDR2 IP core can operate at 266 MHz (533 DDR2) in the fastest speed-grade (-7) when the data width is 64 bits or less and 2 or
fewer chip selects are used. For help with designs running at 266 MHz, contact your local sales office.
Parameter Settings
2
SLICEs LUTs Registers I/O
f
MAX
(MHz)
User Guide Table 3-1 parameter defaults 1261 1490 1530 246 266 MHz (533 DDR2)
LatticeSC/M
1
1. Performance and utilization characteristics are generated using LFSC3GA25E-6F900C Lattice ispLEVER 8.1 software in DDR2 mode.
Performance may vary when using this IP core in a different density, speed or grade within the LatticeSC/M family.
2. SDRAM data path width of 32 bits.
Parameter Settings
2
SLICEs LUTs Registers I/O
f
MAX
(MHz)
User Guide Table 3-1 parameter defaults 704 1325 1118 152 133 MHz (266 DDR2)
MachXO2
1
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