MC74HCT4094ADR2G

MC74HCT4094A
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4
MAXIMUM RATINGS
Symbol Parameter Value Unit
V
CC
DC Supply Voltage (Referenced to GND) – 0.5 to + 7.0 V
V
in
DC Input Voltage (Referenced to GND) – 0.5 to V
CC
+ 0.5 V
V
out
DC Output Voltage (Referenced to GND) – 0.5 to V
CC
+ 0.5 V
I
in
DC Input Current, per Pin ± 20 mA
I
out
DC Output Current, per Pin ± 35 mA
I
CC
DC Supply Current, V
CC
and GND Pins ± 75 mA
P
D
Power Dissipation in Still Air, SOIC Package†
TSSOP Package†
500
450
mW
T
stg
Storage Temperature – 65 to + 150 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect device
reliability.
Derating SOIC Package: – 7 mW/°C from 65° to 125°C
TSSOP Package: 6.1 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
V
CC
DC Supply Voltage (Referenced to GND) 4.5 5.5 V
V
in
, V
out
DC Input Voltage, Output Voltage
(Referenced to GND)
0 V
CC
V
T
A
Operating Temperature, All Package Types –55 +125 °C
t
r
, t
f
Input Rise and Fall Time (Figure 1) 0 500 ns
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this highimpedance cir-
cuit. For proper operation, V
in
and
V
out
should be constrained to the
range GND v (V
in
or V
out
) v V
CC
.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V
CC
).
Unused outputs must be left open.
MC74HCT4094A
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5
FUNCTIONAL TABLE
INPUTS PARALLEL OUTPUTS SERIAL OUTPUTS
CP OE STR D QP0 QPn QS1 QS2
L X X Z Z Q’6 NC
L X X Z Z NC QP7
H L X NC NC Q’6 NC
H H L L QPn1 Q’6 NC
H H H H QPn1 Q’6 NC
H H H NC NC NC QP7
Notes
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
Z = high impedance OFFstate
NC = no change
= LOWtoHIGH CP transition
= HIGHtoLOW CP transition
Q’6 = the information in the seventh register stage is transferred to the 8th register stage and QSn output at the positive clock edge
Figure 6. Timing Diagram
CLOCK INPUT
DATA INPUT
STROBE INPUT
OUTPUT ENABLE INPUT
INTERNAL Q’
0
OUTPUT
INTERNAL Q’
6
OUTPUT
SERIAL OUTPUT
SERIAL OUTPUT
CP
D
STR
OE
FF0
QP
0
FF6
QP6
QS1
QS2
Zstate
Zstate
MC74HCT4094A
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6
DC CHARACTERISTICS
Symbol Parameter Test Conditions V
CC
(V)
Guaranteed Limits
Unit
555C to 255C 855C 1255C
V
IH
Minimum HighLevel Input
Voltage
V
OUT
= 0.1 V or V
CC
– 0.1 V
I
OUT
20 mA
4.5 2.0 2.0 2.0
V
5.5 2.0 2.0 2.0
V
IL
Maximum LowLevel Input
Voltage
V
OUT
= 0.1 V or V
CC
– 0.1 V
I
OUT
20 mA
4.5 0.8 0.8 0.8
V
5.5 0.8 0.8 0.8
V
OH
Minimum HighLevel Output
Voltage
V
IN
= V
IH
or V
IL
I
OUT
20 mA
4.5 4.4 4.4 4.4
V
5.5 5.4 5.4 5.4
V
IN
= V
IH
or V
IL
, I
OUT
= 6 mA 4.5 4.25 4.2 4.1
V
OL
Maximum LowLevel Output
Voltage
V
IN
= V
IH
or V
IL
, I
OUT
20 mA 4.5 0.1 0.1 0.1
V
5.5 0.1 0.1 0.1
V
IN
= V
IH
or V
IL
, I
OUT
= 6 mA 4.5 0.25 0.3 0.4
I
IN
Maximum Input Leakage
Current
V
IN
= V
CC
or GND 5.5 ±0.1 ±1 ±1
mA
I
OZ
Maximum TriState Output
Leakage Current
V
IN
= V
CC
or GND
V
OUT
= V
CC
or GND
5.5 ±0.5 ±5 ±10
mA
I
CC
Maximum Quiescent Supply
Current
V
IN
= V
CC
or GND 5.5 4.0 40 80
mA
DI
CC
Additional Quiescent Supply
Current
V
in
= 2.4V, Any One Input
V
in
= V
CC
or GND, Other Inputs
I
out
= 0mA
5.5
55°C 25 to 125°C
mA
2.9 2.4

MC74HCT4094ADR2G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Counter Shift Registers IC BUS REG TRE-ST 8STG
Lifecycle:
New from this manufacturer.
Delivery:
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