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IS64WV20488BLL-10CTLA3

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
10 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
06/23/2014
IS61WV20488ALL, IS61/64WV20488BLL
t
RC
t
OHA
t
AA
t
DOE
t
LZOE
t
ACE
t
LZCE
t
HZOE
HIGH-Z
DATA VALID
CE_RD2.eps
ADDRESS
OE
CE
D
OUT
t
HZCE
READ CYCLE NO. 2
(1,3)
(CE and OE Controlled)
Notes:
1. WEisHIGHforaReadCycle.
2. Thedeviceiscontinuouslyselected.OE, CE =
VIl.
3. Address is valid prior to or coincident with CELOWtransitions.
AC WAVEFORMS
READ CYCLE NO. 1
(1,2)
(Address Controlled) (CE = OE = VIl)
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 11
Rev. C
06/23/2014
IS61WV20488ALL, IS61/64WV20488BLL
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,3)
(OverOperatingRange)
-8 -10
Symbol Parameter Min. Max. Min. Max. Unit
twc WriteCycleTime 8 — 10 — ns
tsce CEtoWriteEnd 6.5 — 8 — ns
taw AddressSetupTime 6.5 — 8 — ns
toWriteEnd
tha AddressHoldfromWriteEnd 0 — 0 — ns
tsa AddressSetupTime 0 — 0 — ns
tPwe1 WE Pulse Width
(OE = HIGH)
6.5 — 8 — ns
tPwe2 WE Pulse Width (OE=LOW) 8.0 — 10 — ns
tsd DataSetuptoWriteEnd 5 — 6 — ns
thd DataHoldfromWriteEnd 0 — 0 — ns
thzwe
(2)
WELOWtoHigh-ZOutput — 3.5 — 5 ns
tlzwe
(2)
WEHIGHtoLow-ZOutput 2 — 2 — ns
Notes:
1. Testconditionsassumesignaltransitiontimesof3nsorless,timingreferencelevelsof1.5V,inputpulselevelsof0Vto3.0V
andoutputloadingspeciedinFigure1.
2. TestedwiththeloadinFigure2.Transitionismeasured±500mVfromsteady-statevoltage.Not100%tested.
3. TheinternalwritetimeisdenedbytheoverlapofCELOWandWELOW.Allsignalsmustbeinvalidstatestoinitiatea
Write,butanyonecangoinactivetoterminatetheWrite.TheDataInputSetupandHoldtimingarereferencedtotherising
or falling edge of the signal that terminates the write. Shaded area product in development
12 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
06/23/2014
IS61WV20488ALL, IS61/64WV20488BLL
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,2)
(OverOperatingRange)
-20 ns
Symbol Parameter Min. Max. Unit
twc WriteCycleTime 20 — ns
tsce CEtoWriteEnd 12 — ns
taw AddressSetupTime 12 — ns
toWriteEnd
tha AddressHoldfromWriteEnd 0 — ns
tsa AddressSetupTime 0 — ns
tPwe1 WE Pulse Width (OE = HIGH) 12 — ns
tPwe2 WE Pulse Width (OE=LOW) 17 — ns
tsd DataSetuptoWriteEnd 9 — ns
thd DataHoldfromWriteEnd 0 — ns
thzwe
(3)
WELOWtoHigh-ZOutput — 9 ns
tlzwe
(3)
WEHIGHtoLow-ZOutput 3 — ns
Notes:
1. Test conditions assume signal transition times of 1.5ns or less, timing reference levels of 1.25V, input
pulse levels of 0.4V to V
dd-0.3VandoutputloadingspeciedinFigure1.
2. TestedwiththeloadinFigure2.Transitionismeasured±500mVfromsteady-statevoltage.Not100%
tested.
3. TheinternalwritetimeisdenedbytheoverlapofCELOWandWELOW.Allsignalsmustbeinvalid
statestoinitiateaWrite,butanyonecangoinactivetoterminatetheWrite.TheDataInputSetupand
Hold timing are referenced to the rising or falling edge of the signal that terminates the write.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

IS64WV20488BLL-10CTLA3

Mfr. #:
Buy IS64WV20488BLL-10CTLA3
Manufacturer:
ISSI
Description:
SRAM 16Mb 10ns 2.4v-3.6v 2048K x 8 Async SRAM
Lifecycle:
New from this manufacturer.
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