1/9February 2002
■ 3.6V TOLERANT INPUTS AND OUTPUTS
■ HIGH SPEED:
t
PD
= 3.0ns (MAX.) at V
CC
= 3.0 to 3.6V
t
PD
= 3.7ns (MAX.) at V
CC
= 2.3 to 2.7V
■ POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS
■ SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 24mA (MIN) at V
CC
= 3V
|I
OH
| = I
OL
= 8mA (MIN) at V
CC
= 2.3V
■ OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 1.65V to 3.6V
■ PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 32245
■ BUS HOLD PROVIDED ON BOTH SIDE
■ LATCH-UP PERFORMANCE EXCEEDS
300mA
■ ESD PERFORMANCE:
HBM > 2000V (MIL STD 883 method 3015);
MM > 200V
DESCRIPTION
The 74ALVCH32245 is a low voltage CMOS
32-BIT BUS TRANSCEIVER (3-STATE)
fabricated with sub-micron silicon gate and
five-layer metal wiring C
2
MOS technology. It is
ideal for 1.65 to 3.6 V applications; it can be
interfaced to 3.6V signal enviroment for both
inputs and outputs.
This IC is intended for two-ways asynchronous
communication between data buses: the direction
of data trasmission is determined by DIR input.
Any nG
contol output governs eight BUS
TRANSCEIVERS. Output Enable input (nG
) tied
together gives full 32-bit operation. When nG
is
LOW, the output are enabled. When nG
is HIGH,
the output are in high impedance state so that the
buses are effectively isolated. Bus hold on data
inputs is provided in order to eliminate the need for
external pull-up or pull-down resistor.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74ALVCH32245
LOW VOLTAGE CMOS 32-BIT BUS TRANSCEIVER
(3-STATE) WITH 3.6V TOLERANTAT INPUTS AND OUTPUTS
LOGIC DIAGRAM
ORDER CODES
PACKAGE TRAY T & R
LFBGA96 74ALVCH32245LB 74ALVCH32245LBR
LFBGA96
(Top and Bottom view)
Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s)
