IRFP4004PbF
www.irf.com 7
Fig 22a. Switching Time Test Circuit
Fig 22b. Switching Time Waveforms
V
GS
V
DS
90%
10%
t
d(on)
t
d(off)
t
r
t
f
V
GS
Pulse Width < 1µs
Duty Factor < 0.1%
V
DD
V
DS
L
D
D.U.T
+
-
Fig 21b. Unclamped Inductive Waveforms
Fig 21a. Unclamped Inductive Test Circuit
t
p
V
(BR)DSS
I
AS
R
G
I
AS
0.01
Ω
t
p
D.U.T
L
V
DS
+
-
V
DD
DRIVER
15V
20V
V
GS
Fig 23a. Gate Charge Test Circuit
Fig 23b. Gate Charge Waveform
Vds
Vgs
Id
Vgs(th)
Qgs1
Qgs2 Qgd Qgodr
Fig 20. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET
®
Power MOSFETs
1K
VCC
DUT
0
L
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
P.W.
Period
di/dt
Diode Recovery
dv/dt
Ripple ≤ 5%
Body Diode Forward Drop
Re-Applied
Voltage
Reverse
Recovery
Current
Body Diode Forward
Current
V
GS
=10V
V
DD
I
SD
Driver Gate Drive
D.U.T. I
SD
Waveform
D.U.T. V
DS
Waveform
Inductor Curent
D =
P. W .
Period
* V
GS
= 5V for Logic Level Devices
*
+
+
+
-
-
-
R
G
V
DD
• dv/dt controlled by R
G
• Driver same type as D.U.T.
• I
SD
controlled by Duty Factor "D"
• D.U.T. - Device Under Test
D.U.T
Inductor Current
