ISL6506CBZ

7
FN9141.7
November 10, 2015
current demands. Thus, it is recommended that the output
capacitors be selected for transient load regulation, paying
attention to their parasitic components (ESR, ESL).
Also, during the transition between active and sleep states
on the 5V
DUAL
output, there is a short interval of time during
which none of the power pass elements are conducting.
During this time the output capacitors have to supply all the
output current. The output voltage drop during this brief
period of time can be easily approximated using Equation 1:
where:
V
OUT
= output voltage drop
ESR
OUT
= output capacitor bank ESR
I
OUT
= output current during transition
C
OUT
= output capacitor bank capacitance
t
t
= active-to-sleep/sleep-to-active transition time (10µs
typical)
The output voltage drop is heavily dependent on the ESR
(equivalent series resistance) of the output capacitor bank,
the choice of capacitors should be such as to maintain the
output voltage above the lowest allowable regulation level.
Input Capacitors Selection
The input capacitors for an ISL6506, ISL6506A application
must have a sufficiently low ESR so as not to allow the input
voltage to dip excessively when energy is transferred to the
output capacitors. If the ATX supply does not meet the
specifications, certain imbalances between the ATX’s
outputs and the ISL6506, ISL6506As regulation levels could
have as a result a brisk transfer of energy from the input
capacitors to the supplied outputs. At the transition between
active and sleep states, such phenomena could be
responsible for the 5V
SB
voltage drooping excessively and
affecting the output regulation. The solution to such a
potential problem is using larger input capacitors with a
lower total combined ESR.
Transistor Selection/Considerations
The ISL6506, ISL6506A usually requires one P-Channel and
two N-Channel MOSFETs. All three of these MOSFETs are
utilized as ON/OFF switching elements.
One important criteria for selection of transistors for all the
switching elements is package selection for efficient removal
of heat. The power dissipated in a switch element while on is
shown in Equation 2:
Select a package and heatsink that maintains the junction
temperature below the rating with the maximum expected
ambient temperature.
Q1, Q3
These N-Channel MOSFETs are used to switch the 3.3V and
5V inputs provided by the ATX supply into the 3.3V
AUX
and
5V
DUAL
outputs while in active (S0, S1) state. The main
criteria for the selection of these transistors is output voltage
budgeting. The maximum r
DS(ON)
allowed at highest junction
temperature can be expressed using Equation 3:
where:
V
INmin
= minimum input voltage
V
OUTmin
= minimum output voltage allowed
I
OUTmax
= maximum output current
Q2
This is a P-Channel MOSFET used to switch the 5V
SB
output of the ATX supply into the 5V
DUAL
output during
sleep states. The selection criteria of this device, as with the
N-Channel MOSFETs, is proper voltage budgeting. The
maximum r
DS(ON)
, however, has to be achieved with only
4.5V of gate-to-source voltage, so a true logic level
MOSFET needs to be selected.
V
OUT
I
OUT
ESR
OUT
t
t
C
OUT
----------------
+



=
(EQ. 1)
P
LOSS
I
o
2
r
DS ON
=
(EQ. 2)
r
DS ONmax
V
INmin
V
OUTmin
I
OUTmax
---------------------------------------------------
=
(EQ. 3)
ISL6506, ISL6506A, ISL6506B
8
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FN9141.7
November 10, 2015
About Intersil
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For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
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.
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Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make
sure that you have the latest revision.
DATE REVISION CHANGE
November 10, 2015 FN9141.7 - Updated Ordering Information Table on page 1.
- Added Revision History.
- Added About Intersil Verbiage.
ISL6506, ISL6506A, ISL6506B
9
FN9141.7
November 10, 2015
ISL6506, ISL6506A, ISL6506B
Small Outline Exposed Pad Plastic Packages (EPSOIC)
INDEX
AREA
E
D
N
123
-B-
0.25(0.010) C AM BS
e
-A-
L
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
h x 45°
C
H
0.25(0.010) BM M
P1
123
P
BOTTOM VIEW
N
TOP VIEW
SIDE VIEW
M8.15C
8 LEAD NARROW BODY SMALL OUTLINE EXPOSED PAD
PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.056 0.066 1.43 1.68 -
A1 0.001 0.005 0.03 0.13 -
B 0.0138 0.0192 0.35 0.49 9
C 0.0075 0.0098 0.19 0.25 -
D 0.189 0.196 4.80 4.98 3
E 0.150 0.157 3.811 3.99 4
e 0.050 BSC 1.27 BSC -
H 0.230 0.244 5.84 6.20 -
h 0.010 0.016 0.25 0.41 5
L 0.016 0.035 0.41 0.89 6
N8 87
-
P - 0.126 - 3.200 11
P1 - 0.099 - 2.514 11
Rev. 1 6/05
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch
dimensions are not necessarily exact.
11. Dimensions “P” and “P1” are thermal and/or electrical enhanced
variations. Values shown are maximum size of exposed pad
within lead count and body size.

ISL6506CBZ

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Switching Controllers 2 OUTPUT ACPI PWR CNTRLR 8LD EP
Lifecycle:
New from this manufacturer.
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