MAX7325
I
2
C Port Expander with 8 Push-Pull
and 8 Open-Drain I/Os
7
Maxim Integrated
The open-drain ports offer latching transition detection
when used as inputs. All input ports are continuously
monitored for changes. An input change sets one of 8
flag bits that identify changed input(s). All flags are
cleared upon a subsequent read or write transaction to
the MAX7325.
A latching interrupt output, INT, is programmed to flag
logic changes on ports used as inputs. Data changes
on any input port forces INT to a logic-low. Changing
the I/O port level through the serial interface does not
cause an interrupt. The interrupt output INT is deassert-
ed when the MAX7325 is next accessed through the
serial interface.
Internal pullup resistors to V+ are selected by the
address select inputs, AD0 and AD2. Pullups are
enabled on the input ports in groups of four (see Table 2).
Use the slave address selection to ensure that I/O ports
used as inputs are logic-high on power-up. I/O ports
with internal pullups enabled default to a logic-high out-
put state. I/O ports with internal pullups disabled
default to a logic-low output state.
Output port power-up logic levels are selected by the
address select inputs, AD0 and AD2. Ports default to
logic-high or logic-low on power-up in groups of four
(see Tables 2 and 3).
Initial Power-Up
On power-up, the transition detection logic is reset, and
INT is deasserted. The transition flags are cleared to indi-
cate no data changes. The power-up default states of the
16 I/O ports are set according to the I
2
C slave address
selection inputs, AD0 and AD2 (Tables 2 and 3). For I/O
ports used as inputs, ensure that the default states are
logic-high so that the I/O ports power up in the high-
impedance state. All I/O ports configured with pullups
enabled also have a logic-high power-up state.
Power-On Reset
The MAX7325 contains an integral power-on-reset
(POR) circuit that ensures all registers are reset to a
known state on power-up. When V+ rises above V
POR
(1.6V max), the POR circuit releases the registers and
2-wire interface for normal operation. When V+ drops to
less than V
POR
, the MAX7325 resets all register con-
tents to the POR defaults (Tables 2 and 3).
RST
Input
The active-low RST input voids any I
2
C transaction
involving the MAX7325, forcing the MAX7325 into the
I
2
C STOP condition. A reset does not affect the inter-
rupt output (INT).
Standby Mode
When the serial interface is idle, the MAX7325 automatical-
ly enters standby mode, drawing minimal supply current.
Slave Address, Power-Up Default Logic
Levels, and Input Pullup Selection
Address inputs AD0 and AD2 determine the MAX7325
slave address, set the power-up I/O state for the ports,
and select which inputs have pullup resistors. Internal
pullups and power-up default states are set in groups
of four (see Table 2).
The MAX7325 slave address is determined on each I
2
C
transmission, regardless of whether the transmission is
actually addressing the MAX7325. The MAX7325 distin-
guishes whether address inputs AD0 and AD2 are con-
nected to SDA or SCL instead of fixed logic levels V+
or GND during this transmission. The MAX7325 slave
address can be configured dynamically in the applica-
tion without cycling the device supply.
On initial power-up, the MAX7325 cannot decode the
address inputs AD0 and AD2 fully until the first I
2
C
transmission. AD0 and AD2 initially appear to be
detection interrupt and selectable pullups.
levels.
detection interrupt and pullups on all ports.
