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SZESD7016MUTAG

P1-P3P4-P6P7-P8
© Semiconductor Components Industries, LLC, 2013
May, 2013 − Rev. 3
1 Publication Order Number:
ESD7016/D
ESD7016, SZESD7016
Low Capacitance ESD
Protection USB3.0
The ESD7016 transient voltage suppressor is specifically designed
to protect USB3.0 interfaces by integrating two Superspeed pairs, D+,
D−, and Vbus lines into a single protection product. Ultra−low
capacitance and low ESD clamping voltage make this device an ideal
solution for protecting voltage sensitive high speed data lines. The
flow−through style package allows for easy PCB layout and matched
trace lengths necessary to maintain consistent impedance between
high speed differential lines.
Features
• Low Capacitance (0.15 pF Typical, I/O to GND)
• Protection for the Following IEC Standards:
IEC 61000−4−2 (Level 4)
• Low ESD Clamping Voltage
• SZ Prefix for Automotive and Other Applications Requiring Unique
Site and Control Change Requirements; AEC−Q101 Qualified and
PPAP Capable
• This is a Pb−Free Device
Typical Applications
• USB 3.0
MAXIMUM RATINGS (T
J
= 25°C unless otherwise noted)
Rating
Symbol Value Unit
Operating Junction Temperature Range T
J
−55 to +125 °C
Storage Temperature Range T
stg
−55 to +150 °C
Lead Solder Temperature −
Maximum (10 Seconds)
T
L
260 °C
IEC 61000−4−2 Contact (ESD)
IEC 61000−4−2 Air (ESD)
ESD
ESD
±15
±15
kV
kV
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
MARKING
DIAGRAM
Device Package Shipping
ORDERING INFORMATION
http://onsemi.com
ESD7016MUTAG UDFN8
(Pb−Free)
3000 / Tape &
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
1
6M = Specific Device Code
M = Date Code
G = Pb−Free Package
6M MG
G
(Note: Microdot may be in either location)
PIN CONFIGURATION
AND SCHEMATIC
UDFN8
CASE 517CB
N/C
N/C
I/O 1
I/O 2
Vbus or Ground
I/O 3
I/O 4
I/O 5
I/O 6
SZESD7016MUTAG UDFN8
(Pb−Free)
3000 / Tape &
Reel
ESD7016, SZESD7016
http://onsemi.com
2
ELECTRICAL CHARACTERISTICS (T
A
= 25°C unless otherwise specified)
Parameter
Symbol Conditions Min Typ Max Unit
Reverse Working Voltage V
RWM
I/O Pin to GND 5.0 V
Breakdown Voltage V
BR
I
T
= 1 mA, I/O Pin to GND 5.5 V
Reverse Leakage Current I
R
V
RWM
= 5 V, I/O Pin to GND 1.0
mA
Clamping Voltage (Note 1) V
C
I
PP
= 1 A, I/O Pin to GND (8 x 20 ms pulse)
10 V
Clamping Voltage (Note 2) V
C
IEC61000−4−2, ±8 kV Contact See Figures 1 and 2 V
Clamping Voltage
TLP (Note 3)
See Figures 6 through 9
V
C
I
PP
= ±8 A
I
PP
= ±16 A
14.6
20.5
Junction Capacitance C
J
V
R
= 0 V, f = 1 MHz between I/O Pins and GND 0.15 0.20 pF
Junction Capacitance
Difference
DC
J
V
R
= 0 V, f = 1 MHz between I/O Pins and GND 0.03 pF
1. Surge current waveform per Figure 5.
2. For test procedure see Figures 3 and 4 and application note AND8307/D.
3. ANSI/ESD STM5.5.1 − Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model.
TLP conditions: Z
0
= 50 W, t
p
= 100 ns, t
r
= 4 ns, averaging window; t
1
= 30 ns to t
2
= 60 ns.
Figure 1. IEC61000−4−2 +8 KV Contact
Clamping Voltage
Figure 2. IEC61000−4−2 −8 KV Contact
Clamping Voltage
TIME (ns) TIME (ns)
VOLTAGE (V)
VOLTAGE (V)
−10
0
10
20
30
40
50
60
70
80
90
−20 0 20 40 60 80 100 120 140
−100
−80
−60
−40
−20
0
−20 0 20 40 60 80 100 120 140
−90
−70
−50
−30
−10
ESD7016, SZESD7016
http://onsemi.com
3
IEC 61000−4−2 Spec.
Level
Test
Voltage
(kV)
First Peak
Current
(A)
Current at
30 ns (A)
Current at
60 ns (A)
1 2 7.5 4 2
2 4 15 8 4
3 6 22.5 12 6
4 8 30 16 8
I
peak
90%
10%
IEC61000−4−2 Waveform
100%
I @ 30 ns
I @ 60 ns
t
P
= 0.7 ns to 1 ns
Figure 3. IEC61000−4−2 Spec
Figure 4. Diagram of ESD Clamping Voltage Test Setup
50 W
50 W
Cable
TVS
Oscilloscope
ESD Gun
The following is taken from Application Note
AND8308/D − Interpretation of Datasheet Parameters
for ESD Devices.
ESD Voltage Clamping
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since the
IEC61000−4−2 was written as a pass/fail spec for larger
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D and AND8308/D.
Figure 5. 8 X 20 ms Pulse Waveform
100
90
80
70
60
50
40
30
20
10
0
020406080
t, TIME (ms)
% OF PEAK PULSE CURRENT
t
P
t
r
PULSE WIDTH (t
P
) IS DEFINED
AS THAT POINT WHERE THE
PEAK CURRENT DECAY = 8 ms
PEAK VALUE I
RSM
@ 8 ms
HALF VALUE I
RSM
/2 @ 20 ms
P1-P3P4-P6P7-P8

SZESD7016MUTAG

Mfr. #:
Buy SZESD7016MUTAG
Manufacturer:
ON Semiconductor
Description:
TVS Diodes / ESD Suppressors LOW CAP TVS FOR USB
Lifecycle:
New from this manufacturer.
Delivery:
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