MC9S08FL16 Series Data Sheet, Rev. 4
Electrical Characteristics
Freescale Semiconductor20
Figure 10. Typical Crystal or Resonator Circuit
13 C
Long term jitter of DCO output clock (averaged over 2 ms
interval)
8
C
Jitter
— 0.02 0.2
%f
dco
1
Data in Typical column was characterized at 5.0 V, 25 °C or is typical recommended value.
2
When ICS is configured for FEE or FBE mode, input clock source must be divisible using RDIV to within the range of
31.25 kHz to 39.0625 kHz.
3
See crystal or resonator manufacturer’s recommendation.
4
This parameter is characterized and not tested on each device.
5
Proper PC board layout procedures must be followed to achieve specifications.
6
The resulting bus clock frequency should not exceed the maximum specified bus clock frequency of the device.
7
This specification applies to any time the FLL reference source or reference divider is changed, trim value changed, DMX32
bit is changed, DRS bit is changed, or changing from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If
a crystal/resonator is being used as the reference, this specification assumes it is already running.
8
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f
Bus
.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the FLL circuitry via V
DD
and V
SS
and variation in crystal oscillator frequency increase the C
Jitter
percentage for
a given interval.
Table 9. XOSC and ICS Specifications (Temperature Range = –40 to 85 °C Ambient) (continued)
Num C Characteristic Symbol Min Typical
1
Max Unit
XOSC
EXTAL XTAL
Crystal or Resonator
R
S
C
2
R
F
C
1
